Searched full:hardwired (Results 1 – 25 of 134) sorted by relevance
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| /linux-6.12.1/Documentation/hwmon/ |
| D | amc6821.rst | 63 pwm1_auto_point1_pwm ro Hardwired to 0, shared for both
67 pwm1_auto_point3_pwm rw Hardwired to 255, shared for both
70 temp1_auto_point1_temp ro Hardwired to temp2_auto_point1_temp
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| D | adm1025.rst | 44 One specificity of this chip is that the pin 11 can be hardwired in two
49 register can be used to define how the chip is hardwired. Please note that
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| /linux-6.12.1/drivers/clk/versatile/ |
| D | clk-icst.c | 75 * r is hardwired to 22 and output divider s is hardwired to 1 in vco_get()
90 * and always zero, r is hardwired to 46, and the output divider is in vco_get()
91 * hardwired to 3 (divide by 4) according to the document in vco_get()
105 * to select between two different hardwired values: setting the in vco_get()
122 * r is hardwired to 22 and the output divider s is accessible in vco_get()
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| /linux-6.12.1/Documentation/devicetree/bindings/leds/ |
| D | richtek,rt8515.yaml | 59 is hardwired to the component using the RFS resistor to
71 is hardwired to the component using the RTS resistor to
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| /linux-6.12.1/Documentation/devicetree/bindings/sound/ |
| D | adi,adau7002.yaml | 22 hardwired to always on.
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| D | adi,ssm2518.yaml | 29 it is assumed that the nSD pin is hardwired to always on.
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| D | serial-midi.yaml | 16 or other connector, or to a known hardwired MIDI controller. This device must be a
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| /linux-6.12.1/tools/testing/selftests/alsa/conf.d/ |
| D | Lenovo_ThinkPad_P1_Gen2.conf | 8 # The sysfs root directory (/sys) is hardwired in the test code
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| /linux-6.12.1/Documentation/devicetree/bindings/mailbox/ |
| D | amlogic,meson-gxbb-mhu.yaml | 16 MHU links are hardwired on a platform. A link raises interrupt for any
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| D | arm,mhu.yaml | 15 are hardwired on a platform. A link raises interrupt for any received data.
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| /linux-6.12.1/arch/sparc/kernel/ |
| D | iommu_common.h | 32 * This is the hardwired shift in the iotlb tag/data parts.
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | mstar,mst-intc.yaml | 36 lines that are hardwired to mstar interrupt controller.
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| /linux-6.12.1/tools/testing/selftests/rcutorture/doc/ |
| D | TREE_RCU-kconfig.txt | 14 CONFIG_PROVE_RCU -- Hardwired to CONFIG_PROVE_LOCKING.
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| /linux-6.12.1/Documentation/devicetree/bindings/net/can/ |
| D | tcan4x5x.txt | 24 - reset-gpios: Hardwired output GPIO. If not defined then software
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| /linux-6.12.1/Documentation/devicetree/bindings/gpio/ |
| D | gpio-max3191x.txt | 32 is hardwired and consequently "maxim,modesel-gpios"
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/opp/dcn20/ |
| D | dcn20_opp.c | 164 /* DPG_COLOUR registers are 16-bit MSB aligned value with bits 3:0 hardwired to ZERO. in opp2_set_disp_pattern_generator()
311 /* 16-bit MSB aligned value. Bits 3:0 of this field are hardwired to ZERO */ in opp2_dpg_set_blank_color()
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| /linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| D | gm107.c | 29 /* nothing to do, it seems hardwired */ in gm107_fan_pwm_ctrl()
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| D | gf119.c | 63 /* nothing to do for indx == 2, it seems hardwired to PTHERM */ in gf119_fan_pwm_ctrl()
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| /linux-6.12.1/drivers/mmc/core/ |
| D | Kconfig | 63 hardwired device numbering.
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| /linux-6.12.1/arch/arm/boot/dts/allwinner/ |
| D | sunxi-d1s-t113-mangopi-mq-r.dtsi | 117 /* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */
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| /linux-6.12.1/drivers/reset/ |
| D | reset-raspberrypi.c | 48 * But since rpi's PCIe is hardwired, we know the address in in rpi_reset_reset()
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| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3566-soquartz-model-a.dts | 175 * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys,
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| /linux-6.12.1/drivers/gpio/ |
| D | gpio-tps65218.c | 148 /* GPO1 is hardwired to be open drain */ in tps65218_gpio_set_config()
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| /linux-6.12.1/drivers/usb/core/ |
| D | of.c | 116 /* Only set connect_type if binding has ports/hardwired devices. */ in usb_of_get_connect_type()
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| /linux-6.12.1/Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ltc2664.yaml | 50 hardwired option chosen using the MSPAN pins. The control registers are
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