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/linux-6.12.1/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
15 only supports one period for all channels in the PWM. All PWMs need to
18 achievable period. PWM RTL that corresponds to the IP block version
19 numbers can be found here -
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/linux-6.12.1/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
15 "sifive,fu540";
18 stdout-path = "serial0";
22 timebase-frequency = <RTCCLK_FREQ>;
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Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/linux-6.12.1/drivers/pwm/
Dpwm-sifive.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
8 * - When changing both duty cycle and period, we cannot prevent in
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
19 #include <linux/pwm.h>
60 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm) in pwm_sifive_request() argument
64 mutex_lock(&ddata->lock); in pwm_sifive_request()
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/linux-6.12.1/drivers/tty/serial/
Dsifive.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2018-2019 SiFive
8 * - drivers/tty/serial/pxa.c
9 * - drivers/tty/serial/amba-pl011.c
10 * - drivers/tty/serial/uartlite.c
11 * - drivers/tty/serial/omap-serial.c
12 * - drivers/pwm/pwm-sifive.c
15 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
16 * SiFive FE310-G000 v2p3
17 * - The tree/master/src/main/scala/devices/uart directory of
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