/linux-6.12.1/Documentation/devicetree/bindings/net/ |
D | samsung-sxgbe.txt | 4 - compatible: Should be "samsung,sxgbe-v2.0a" 5 - reg: Address and length of the register set for the device 6 - interrupts: Should contain the SXGBE interrupts 7 These interrupts are ordered by fixed and follows variable 9 index 0 - this is fixed common interrupt of SXGBE and it is always 11 index 1 to 25 - 8 variable transmit interrupts, variable 16 receive interrupts 13 - phy-mode: String, operation mode of the PHY interface. 15 - samsung,pbl: Integer, Programmable Burst Length. 17 - samsung,burst-map: Integer, Program the possible bursts supported by sxgbe 18 This is an integer and represents allowable DMA bursts when fixed burst. [all …]
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D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Alexandre Torgue <alexandre.torgue@foss.st.com> 11 - Giuseppe Cavallaro <peppe.cavallaro@st.com> 12 - Jose Abreu <joabreu@synopsys.com> 23 - snps,dwmac 24 - snps,dwmac-3.40a 25 - snps,dwmac-3.50a 26 - snps,dwmac-3.610 [all …]
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D | snps,dwc-qos-ethernet.txt | 13 - compatible: One of: 14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10" 15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC. 16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10" 18 - "snps,dwc-qos-ethernet-4.10" 20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be 22 - reg: Address and length of the register set for the device 23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the 24 same order. See ../clock/clock-bindings.txt. 25 - clock-names: May contain any/all of the following depending on the IP [all …]
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D | ibm,emac.txt | 8 correct clock-frequency property. 13 - device_type : "network" 15 - compatible : compatible list, contains 2 entries, first is 16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx, 18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon", 20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ> 21 - reg : <registers mapping> 22 - local-mac-address : 6 bytes, MAC address 23 - mal-device : phandle of the associated McMAL node 24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/dma/stm32/ |
D | st,stm32-dma3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 22 described in "#dma-cells" property description below, using a three-cell 26 - Amelie Delaunay <amelie.delaunay@foss.st.com> 29 - $ref: /schemas/dma/dma-controller.yaml# 33 const: st,stm32mp25-dma3 42 Should contain all of the per-channel DMA interrupts in ascending order 51 power-domains: [all …]
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/linux-6.12.1/samples/pktgen/ |
D | pktgen_sample05_flow_per_thread.sh | 2 # SPDX-License-Identifier: GPL-2.0 4 # Script will generate one flow per thread (-t N) 5 # - Same destination IP 6 # - Fake source IPs for each flow (fixed based on thread number) 10 # separate-flow should not access shared variables/data. This script 24 if [ -z "$DEST_IP" ]; then 25 [ -z "$IP6" ] && DEST_IP="198.18.0.42" || DEST_IP="FD00::1" 27 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff" 28 [ -z "$CLONE_SKB" ] && CLONE_SKB="0" 29 [ -z "$BURST" ] && BURST=32 [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/dma/ |
D | intel,ldma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - chuanhua.lei@intel.com 11 - mallikarjunax.reddy@intel.com 14 - $ref: dma-controller.yaml# 19 - intel,lgm-cdma 20 - intel,lgm-dma2tx 21 - intel,lgm-dma1rx 22 - intel,lgm-dma1tx [all …]
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/linux-6.12.1/drivers/char/tpm/ |
D | tpm_tis_i2c_cr50.c | 1 // SPDX-License-Identifier: GPL-2.0 10 * - Use an interrupt for transaction status instead of hardcoded delays. 11 * - Must use write+wait+read read protocol. 12 * - All 4 bytes of status register must be read/written at once. 13 * - Burst count max is 63 bytes, and burst count behaves slightly differently 15 * - When reading from FIFO the full burstcnt must be read instead of just 45 * struct tpm_i2c_cr50_priv_data - Driver private data. 47 * If irq <= 0, then a fixed timeout is used instead of waiting for irq. 60 * tpm_cr50_i2c_int_handler() - cr50 interrupt handler. 66 * processing but is instead used to avoid fixed delays. [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | imx8dxl-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 /delete-node/ &enet1_lpcg; 7 /delete-node/ &fec2; 10 conn_enet0_root_clk: clock-conn-enet0-root { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <250000000>; 14 clock-output-names = "conn_enet0_root_clk"; 17 clk_dummy: clock-dummy { 18 compatible = "fixed-clock"; [all …]
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D | imx8ulp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/imx8ulp-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/power/imx8ulp-power.h> 10 #include <dt-bindings/thermal/thermal.h> 12 #include "imx8ulp-pinfunc.h" 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; [all …]
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D | imx8-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 10 conn_axi_clk: clock-conn-axi { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <333333333>; 14 clock-output-names = "conn_axi_clk"; 17 conn_ahb_clk: clock-conn-ahb { [all …]
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/linux-6.12.1/drivers/gpu/drm/nouveau/dispnv04/ |
D | arb.c | 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2007-2009 Stuart Bennett 38 int burst; member 63 pclk_freq = arb->pclk_khz; in nv04_calc_arb() 64 mclk_freq = arb->mclk_khz; in nv04_calc_arb() 65 nvclk_freq = arb->nvclk_khz; in nv04_calc_arb() 66 pagemiss = arb->mem_page_miss; in nv04_calc_arb() 67 cas = arb->mem_latency; in nv04_calc_arb() 68 bpp = arb->bpp; in nv04_calc_arb() 92 m1 = clwm + cbs - 512; in nv04_calc_arb() [all …]
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/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/ |
D | dwmac1000_dma.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs. 9 Copyright (C) 2007-2009 STMicroelectronics Ltd 24 pr_info("dwmac1000: Master AXI performs %s burst length\n", in dwmac1000_dma_axi() 25 !(value & DMA_AXI_UNDEF) ? "fixed" : "any"); in dwmac1000_dma_axi() 27 if (axi->axi_lpi_en) in dwmac1000_dma_axi() 29 if (axi->axi_xit_frm) in dwmac1000_dma_axi() 33 value |= (axi->axi_wr_osr_lmt & DMA_AXI_WR_OSR_LMT_MASK) << in dwmac1000_dma_axi() 37 value |= (axi->axi_rd_osr_lmt & DMA_AXI_RD_OSR_LMT_MASK) << in dwmac1000_dma_axi() 40 /* Depending on the UNDEF bit the Master AXI will perform any burst in dwmac1000_dma_axi() [all …]
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D | dwmac1000.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 Copyright (C) 2007-2009 STMicroelectronics Ltd 23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ 79 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \ 81 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \ 108 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */ 119 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ 177 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */ 196 /*--- DMA BLOCK defines ---*/ 201 /* Programmable burst length (passed thorugh platform)*/ [all …]
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/linux-6.12.1/arch/arm64/boot/dts/xilinx/ |
D | zynqmp-zc1751-xm017-dc3.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm017-dc3 5 * (C) Copyright 2016 - 2021, Xilinx, Inc. 10 /dts-v1/; 13 #include "zynqmp-clk-ccf.dtsi" 14 #include <dt-bindings/phy/phy.h> 17 model = "ZynqMP zc1751-xm017-dc3 RevA"; 18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp"; 34 stdout-path = "serial0:115200n8"; 43 compatible = "fixed-clock"; [all …]
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D | zynqmp-sck-kv-g-revA.dtso | 1 // SPDX-License-Identifier: GPL-2.0 5 * (C) Copyright 2020 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 9 * "A" - A01 board un-modified (NXP) 10 * "Y" - A01 board modified with legacy interposer (Nexperia) 11 * "Z" - A01 board modified with Diode interposer 16 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/net/ti-dp83867.h> 18 #include <dt-bindings/phy/phy.h> 19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> [all …]
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D | zynqmp-zc1751-xm015-dc1.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1 5 * (C) Copyright 2015 - 2022, Xilinx, Inc. 6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. 11 /dts-v1/; 14 #include "zynqmp-clk-ccf.dtsi" 15 #include <dt-bindings/phy/phy.h> 16 #include <dt-bindings/gpio/gpio.h> 17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> 20 model = "ZynqMP zc1751-xm015-dc1 RevA"; [all …]
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/linux-6.12.1/drivers/spi/ |
D | spi-meson-spicc.c | 7 * SPDX-License-Identifier: GPL-2.0+ 12 #include <linux/clk-provider.h> 30 * - all transfers are cutted in 16 words burst because the FIFO hangs on 31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by 33 * - CS management is dumb, and goes UP between every burst, so is really a 69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */ 72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */ 89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */ 92 #define SPICC_RH BIT(4) /* RX FIFO Half-Full Interrupt */ 104 #define SPICC_LBC_RO BIT(13) /* Loop Back Control Read-Only */ [all …]
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
D | omap3-n950-n9.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff) 13 cpu0-supply = <&vcc>; 23 compatible = "regulator-fixed"; 24 regulator-name = "VEMMC"; 25 regulator-min-microvolt = <2900000>; 26 regulator-max-microvolt = <2900000>; 28 startup-delay-us = <150>; 29 enable-active-high; 33 compatible = "regulator-fixed"; [all …]
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D | omap-gpmc-smsc911x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 10 vddvario: regulator-vddvario { 11 compatible = "regulator-fixed"; 12 regulator-name = "vddvario"; 13 regulator-always-on; 16 vdd33a: regulator-vdd33a { 17 compatible = "regulator-fixed"; 18 regulator-name = "vdd33a"; 19 regulator-always-on; 26 bank-width = <2>; [all …]
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D | omap-gpmc-smsc9221.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 14 vddvario: regulator-vddvario { 15 compatible = "regulator-fixed"; 16 regulator-name = "vddvario"; 17 regulator-always-on; 20 vdd33a: regulator-vdd33a { 21 compatible = "regulator-fixed"; 22 regulator-name = "vdd33a"; 23 regulator-always-on; 30 bank-width = <2>; [all …]
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D | omap3-igep.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 8 /dts-v1/; 19 stdout-path = &uart3; 23 compatible = "ti,omap-twl4030"; 28 vdd33: regulator-vdd33 { 29 compatible = "regulator-fixed"; 30 regulator-name = "vdd33"; 31 regulator-always-on; 37 gpmc_pins: gpmc-pins { 38 pinctrl-single,pins = < [all …]
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/linux-6.12.1/arch/arm/boot/dts/nxp/imx/ |
D | imx7ulp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright 2017-2018 NXP 8 #include <dt-bindings/clock/imx7ulp-clock.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include "imx7ulp-pinfunc.h" 15 interrupt-parent = <&intc>; 17 #address-cells = <1>; 18 #size-cells = <1>; 37 #address-cells = <1>; [all …]
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/linux-6.12.1/drivers/net/ethernet/toshiba/ |
D | spider_net.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * Network device driver for Cell Processor-Based Blade and Celleb platform 187 * 0000000 fixed to 0 189 * 000000 fixed to 0 193 * 000000 fixed to 0 194 * 00 burst alignment: 128 bytes 195 * 11 burst alignment: 1024 bytes 197 * 00000 fixed to 0
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/linux-6.12.1/Documentation/networking/device_drivers/ethernet/stmicro/ |
D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+ 13 - In This Release 14 - Feature List 15 - Kernel Configuration 16 - Command Line Parameters 17 - Driver Information and Notes 18 - Debug Information 19 - Support 33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0 35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores [all …]
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