| /linux-6.12.1/arch/arm/mach-shmobile/ |
| D | setup-rcar-gen2.c | 26 { .compatible = "renesas,r8a7742-cpg-mssr", .data = "extal" },
27 { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
28 { .compatible = "renesas,r8a7744-cpg-mssr", .data = "extal" },
29 { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
30 { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
31 { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
38 struct device_node *cpg, *extal; in get_extal_freq() local
48 extal = of_parse_phandle(cpg, "clocks", idx); in get_extal_freq()
50 if (!extal) in get_extal_freq()
53 of_property_read_u32(extal, "clock-frequency", &freq); in get_extal_freq()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/display/bridge/ |
| D | renesas,lvds.yaml | 100 - description: EXTAL input clock
108 # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
111 - extal
115 - extal
119 - extal
181 clock-names = "fck", "dclkin.0", "extal";
212 clock-names = "fck", "dclkin.0", "extal";
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| /linux-6.12.1/drivers/clk/renesas/ |
| D | rcar-usb2-clock-sel.c | 39 bool extal; member
49 priv->extal, priv->xtal, val); in usb2_clock_sel_enable_extal_only()
51 if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY) in usb2_clock_sel_enable_extal_only()
57 if (priv->extal && !priv->xtal) in usb2_clock_sel_disable_extal_only()
164 priv->extal = !!clk_get_rate(clk); in rcar_usb2_clock_sel_probe()
173 if (!priv->extal && !priv->xtal) { in rcar_usb2_clock_sel_probe()
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| D | r8a77470-cpg-mssr.c | 39 DEF_INPUT("extal", CLK_EXTAL),
173 * MD EXTAL PLL0 PLL1 PLL3
188 /* EXTAL div PLL1 mult x2 PLL3 mult */
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| D | r8a779f0-cpg-mssr.c | 56 DEF_INPUT("extal", CLK_EXTAL),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
191 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
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| D | r8a77970-cpg-mssr.c | 65 DEF_INPUT("extal", CLK_EXTAL),
177 * MD EXTAL PLL0 PLL1 PLL3
194 /* EXTAL div PLL1 mult/div PLL3 mult/div */
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| D | r8a77995-cpg-mssr.c | 55 DEF_INPUT("extal", CLK_EXTAL),
211 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
219 /* EXTAL div PLL1 mult/div PLL3 mult/div */
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| D | r8a7745-cpg-mssr.c | 39 DEF_INPUT("extal", CLK_EXTAL),
190 * MD EXTAL PLL0 PLL1 PLL3
205 /* EXTAL div PLL1 mult PLL3 mult PLL0 mult */
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| D | r8a77980-cpg-mssr.c | 53 DEF_INPUT("extal", CLK_EXTAL),
211 * MD EXTAL PLL2 PLL1 PLL3 OSC
223 /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
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| D | r8a774c0-cpg-mssr.c | 57 DEF_INPUT("extal", CLK_EXTAL),
261 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
269 /* EXTAL div PLL1 mult/div PLL3 mult/div */
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| D | r8a7743-cpg-mssr.c | 40 DEF_INPUT("extal", CLK_EXTAL),
206 * MD EXTAL PLL0 PLL1 PLL3
225 /* EXTAL div PLL1 mult PLL3 mult */
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| D | r8a7742-cpg-mssr.c | 39 DEF_INPUT("extal", CLK_EXTAL),
212 * MD EXTAL PLL0 PLL1 PLL3
231 /* EXTAL div PLL1 mult PLL3 mult */
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| D | r8a779a0-cpg-mssr.c | 71 DEF_INPUT("extal", CLK_EXTAL),
251 * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC
262 /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
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| D | r7s9210-cpg-mssr.c | 59 DEF_INPUT("extal", CLK_EXTAL),
120 /* If EXTAL is above 12MHz, then we know it is Mode 1 */ in r7s9210_update_clk_table()
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| D | r8a77990-cpg-mssr.c | 57 DEF_INPUT("extal", CLK_EXTAL),
275 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
283 /* EXTAL div PLL1 mult/div PLL3 mult/div */
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| /linux-6.12.1/Documentation/devicetree/bindings/rtc/ |
| D | renesas,sh-rtc.yaml | 44 enum: [ fck, rtc_x1, rtc_x3, extal ]
76 clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
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| /linux-6.12.1/Documentation/devicetree/bindings/sound/ |
| D | fsl,esai.yaml | 55 - const: extal
112 clock-names = "core", "extal", "fsys";
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | renesas,rzg2l-cpg.yaml | 43 const: extal
101 clock-names = "extal";
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| D | renesas,cpg-mssr.yaml | 68 - extal # All
122 clock-names = "extal", "extalr";
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| /linux-6.12.1/arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7722.c | 42 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
172 CLKDEV_CON_ID("extal", &extal_clk),
224 /* autodetect extal or dll configuration */ in arch_clk_init()
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| D | clock-sh7366.c | 39 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
186 CLKDEV_CON_ID("extal", &extal_clk),
249 /* autodetect extal or dll configuration */ in arch_clk_init()
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| D | clock-sh7343.c | 39 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
188 CLKDEV_CON_ID("extal", &extal_clk),
256 /* autodetect extal or dll configuration */ in arch_clk_init()
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| /linux-6.12.1/drivers/gpu/drm/renesas/rcar-du/ |
| D | rcar_lvds.c | 75 struct clk *extal; /* External clock */ member
282 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll, in rcar_lvds_pll_setup_d3_e3()
838 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true); in rcar_lvds_get_clocks()
839 if (IS_ERR(lvds->clocks.extal)) in rcar_lvds_get_clocks()
840 return PTR_ERR(lvds->clocks.extal); in rcar_lvds_get_clocks()
851 if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] && in rcar_lvds_get_clocks()
854 "no input clock (extal, dclkin.0 or dclkin.1)\n"); in rcar_lvds_get_clocks()
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| /linux-6.12.1/arch/sh/boards/ |
| D | board-urquell.c | 184 * Only handle the EXTAL case, anyone interfacing a crystal in urquell_clk_init()
190 clk = clk_get(NULL, "extal"); in urquell_clk_init()
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| /linux-6.12.1/arch/sh/boards/mach-sdk7786/ |
| D | setup.c | 195 * Only handle the EXTAL case, anyone interfacing a crystal in sdk7786_clk_init()
201 clk = clk_get(NULL, "extal"); in sdk7786_clk_init()
|