| /linux-6.12.1/Documentation/devicetree/bindings/iio/imu/ |
| D | adi,adis16480.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - adi,adis16375
16 - adi,adis16480
17 - adi,adis16485
18 - adi,adis16488
19 - adi,adis16490
20 - adi,adis16495-1
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/rtc/ |
| D | rtc-omap.txt | 4 - compatible:
5 - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
6 - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
7 This RTC IP has special WAKE-EN Register to enable
10 pmic_power_en pin.
11 - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
12 - reg: Address range of rtc register set
13 - interrupts: rtc timer, alarm interrupts in order
16 - system-power-controller: whether the rtc is controlling the system power
18 - clocks: Any internal or external clocks feeding in to rtc
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/samsung/ |
| D | exynos4x12-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source
8 * Samsung's Exynos4x12 SoCs pin-mux and pin-config options are listed as device
12 #include "exynos-pinctrl.h"
15 pin- ## _pin { \
17 samsung,pin-con-pdn = <EXYNOS_PIN_PDN_ ##_mode>; \
18 samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_ ##_pull>; \
22 gpa0: gpa0-gpio-bank {
23 gpio-controller;
24 #gpio-cells = <2>;
[all …]
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| D | s5pv210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S5PV210 SoC device tree source - pin control-related
6 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
11 * Samsung's S5PV210 SoC pin banks, pin-mux and pin-config options are
15 #include "s5pv210-pinctrl.h"
18 pin- ## _pin { \
20 samsung,pin-con-pdn = <S5PV210_PIN_PDN_ ##_mode>; \
21 samsung,pin-pud-pdn = <S5PV210_PIN_PULL_ ##_pull>; \
25 gpa0: gpa0-gpio-bank {
26 gpio-controller;
[all …]
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| D | exynos4210-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos4210 SoC pin-mux and pin-config device tree source
5 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2011-2012 Linaro Ltd.
10 * Samsung's Exynos4210 SoC pin-mux and pin-config options are listed as device
14 #include "exynos-pinctrl.h"
17 gpa0: gpa0-gpio-bank {
18 gpio-controller;
19 #gpio-cells = <2>;
21 interrupt-controller;
[all …]
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| D | exynos3250-artik5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
26 stdout-path = &serial_2;
35 compatible = "samsung,secure-firmware";
39 thermal-zones {
40 cpu_thermal: cpu-thermal {
41 cooling-maps {
44 cooling-device = <&cpu0 5 5>,
[all …]
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| D | s3c64xx-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 * - pin control-related definitions
8 * Samsung's S3C64xx SoCs pin banks, pin-mux and pin-config options are
12 #include "s3c64xx-pinctrl.h"
16 * Pin banks
19 gpa: gpa-gpio-bank {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
[all …]
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| D | exynos5250-snow-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/samsung-i2s.h>
30 stdout-path = "serial3:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | sti-dwmac.txt | 10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
26 - sti-ethclk: this is the phy clock.
27 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
28 to program the clk retiming.
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad4130.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Cosmin Tanislav <cosmin.tanislav@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-8.pdf
20 - adi,ad4130
29 clock-names:
31 - const: mclk
36 interrupt-names:
38 Specify which interrupt pin should be configured as Data Ready / FIFO
[all …]
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| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | imx8mq-nitrogen.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
16 stdout-path = "serial0:115200n8";
24 gpio-keys {
25 compatible = "gpio-keys";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_keys>;
29 button-power {
[all …]
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| /linux-6.12.1/drivers/clk/ |
| D | clk-palmas.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2013-2014 Texas Instruments, Inc.
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
57 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, in palmas_clks_prepare()
58 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
59 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
60 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
62 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", in palmas_clks_prepare()
63 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
[all …]
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| /linux-6.12.1/arch/sh/include/cpu-sh4/cpu/ |
| D | sh7785.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1]
8 * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1]
9 * MODE2: CPG - Reserved (L: Normal operation)
10 * MODE3: CPG - Reserved (L: Normal operation)
11 * MODE4: CPG - Initial PLL setting (72x/36x)
12 * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
13 * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
14 * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
15 * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
[all …]
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| /linux-6.12.1/drivers/clk/sprd/ |
| D | ums512-clk.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/sprd,ums512-clk.h>
33 static CLK_FIXED_FACTOR_FW_NAME(clk_26m_aud, "clk-26m-aud", "ext-26m", 1, 1, 0);
34 static CLK_FIXED_FACTOR_FW_NAME(clk_13m, "clk-13m", "ext-26m", 2, 1, 0);
35 static CLK_FIXED_FACTOR_FW_NAME(clk_6m5, "clk-6m5", "ext-26m", 4, 1, 0);
36 static CLK_FIXED_FACTOR_FW_NAME(clk_4m3, "clk-4m3", "ext-26m", 6, 1, 0);
37 static CLK_FIXED_FACTOR_FW_NAME(clk_2m, "clk-2m", "ext-26m", 13, 1, 0);
38 static CLK_FIXED_FACTOR_FW_NAME(clk_1m, "clk-1m", "ext-26m", 26, 1, 0);
39 static CLK_FIXED_FACTOR_FW_NAME(clk_250k, "clk-250k", "ext-26m", 104, 1, 0);
[all …]
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| D | sc9863a-clk.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
26 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
28 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
30 static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
32 static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
34 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
36 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
38 static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
[all …]
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| /linux-6.12.1/drivers/comedi/drivers/ |
| D | amplc_dio200.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
[all …]
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| /linux-6.12.1/sound/soc/intel/boards/ |
| D | cht_bsw_rt5672.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
16 #include <linux/clk.h>
21 #include <sound/soc-acpi.h>
23 #include "../atom/sst-atom-controls.h"
24 #include "../common/soc-intel-quirks.h"
29 #define CHT_CODEC_DAI "rt5670-aif1"
34 struct clk *mclk;
41 .pin = "Headset Mic",
45 .pin = "Headphone",
[all …]
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| D | sof_pcm512x.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright(c) 2018-2020 Intel Corporation.
8 #include <linux/clk.h>
20 #include <sound/soc-acpi.h>
22 #include "../common/soc-intel-quirks.h"
55 sof_pcm512x_quirk = (unsigned long)id->driver_data; in sof_pcm512x_quirk_cb()
64 DMI_MATCH(DMI_PRODUCT_NAME, "UP-CHT01"),
73 struct sof_card_private *ctx = snd_soc_card_get_drvdata(rtd->card); in sof_hdmi_init()
77 pcm = devm_kzalloc(rtd->card->dev, sizeof(*pcm), GFP_KERNEL); in sof_hdmi_init()
79 return -ENOMEM; in sof_hdmi_init()
[all …]
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| D | cht_bsw_max98090_ti.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht-bsw-max98090.c - ASoc Machine driver for Intel Cherryview-based
20 #include <linux/clk.h>
24 #include <sound/soc-acpi.h>
27 #include "../atom/sst-atom-controls.h"
36 struct clk *mclk;
45 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
46 struct snd_soc_card *card = dapm->card; in platform_clock_control()
52 if (ctx->quirks & QUIRK_PMC_PLT_CLK_0) in platform_clock_control()
57 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); in platform_clock_control()
[all …]
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| D | cht_bsw_rt5645.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * cht-bsw-rt5645.c - ASoc Machine driver for Intel Cherryview-based platforms
18 #include <linux/clk.h>
25 #include <sound/soc-acpi.h>
27 #include "../atom/sst-atom-controls.h"
28 #include "../common/soc-intel-quirks.h"
31 #define CHT_CODEC_DAI1 "rt5645-aif1"
32 #define CHT_CODEC_DAI2 "rt5645-aif2"
43 struct clk *mclk;
69 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
[all …]
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| /linux-6.12.1/drivers/iio/imu/ |
| D | adis16480.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk.h>
116 ADIS16480_REG((page) + 1, (x) - 60 + 8))
176 struct clk *ext_clk;
194 … "Allow IMU rates below the minimum advisable when external clk is used in PPS mode (default: N)");
199 struct adis16480 *adis16480 = file->private_data; in adis16480_show_firmware_revision()
205 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_REV, &rev); in adis16480_show_firmware_revision()
224 struct adis16480 *adis16480 = file->private_data; in adis16480_show_firmware_date()
230 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_Y, &year); in adis16480_show_firmware_date()
234 ret = adis_read_reg_16(&adis16480->adis, ADIS16480_REG_FIRM_DM, &md); in adis16480_show_firmware_date()
[all …]
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| /linux-6.12.1/sound/soc/ti/ |
| D | omap-abe-twl6040.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap-abe-twl6040.c -- SoC audio for TI OMAP based boards with ABE and
9 #include <linux/clk.h>
20 #include "omap-dmic.h"
21 #include "omap-mcpdm.h"
26 DAILINK_COMP_ARRAY(COMP_CODEC("twl6040-codec",
27 "twl6040-legacy")),
32 DAILINK_COMP_ARRAY(COMP_CODEC("dmic-codec",
33 "dmic-hifi")),
50 struct snd_soc_card *card = rtd->card; in omap_abe_hw_params()
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/st/ |
| D | ste-snowball.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011 ST-Ericsson AB
6 /dts-v1/;
7 #include "ste-db9500.dtsi"
8 #include "ste-href-ab8500.dtsi"
9 #include "ste-href-family-pinctrl.dtsi"
13 compatible = "calaosystems,snowball-a9500", "st-ericsson,u9500";
21 compatible = "simple-battery";
22 battery-type = "lithium-ion-polymer";
25 thermal-zones {
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/allwinner/ |
| D | sun8i-a23-a33.dtsi | 2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun6i-rtc.h>
48 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
49 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <1>;
[all …]
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| /linux-6.12.1/arch/arm64/boot/dts/renesas/ |
| D | rzg2l-smarc-pinfunction.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
25 line-name = "can0_stb";
[all …]
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