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/linux-6.12.1/Documentation/devicetree/bindings/net/
Drealtek,rtl82xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek RTL82xx PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id001c.c800
21 - ethernet-phy-id001c.c816
22 - ethernet-phy-id001c.c838
[all …]
Dnxp,tja11xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP TJA11xx PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
[all …]
Dmarvell,aquantia.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Aquantia Ethernet PHY
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Marvell Aquantia Ethernet PHY require a firmware to be loaded to actually
17 - Attached SPI flash directly to the PHY with the firmware. The PHY
19 - Read from a dedicated partition on system NAND declared in an
20 NVMEM cell, and loaded to the PHY using its mailbox interface.
21 - Manually provided firmware loaded from a file in the filesystem.
[all …]
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Common Properties
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
[all …]
Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
11 provides connectivity to an external ethernet PHY supporting different
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
[all …]
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
57 ethernet@e0000 {
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
62 ethernet@e2000 {
63 phy-handle = <&phy_sgmii_s7_1d>;
[all …]
Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
65 ethernet@e0000 {
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
70 ethernet@e2000 {
71 phy-handle = <&phy_sgmii_s3_1f>;
[all …]
Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
59 ethernet@e0000 {
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
64 ethernet@e2000 {
[all …]
Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fqd {
[all …]
Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
Dtqmls104xa-mbls10xxa-fman.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2019,2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
10 #include <dt-bindings/net/ti-dp83867.h>
21 phy-handle = <&rgmii_phy1>;
22 phy-connection-type = "rgmii";
23 phy-mode = "rgmii-id";
28 phy-handle = <&rgmii_phy2>;
29 phy-connection-type = "rgmii";
30 phy-mode = "rgmii-id";
[all …]
Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
Dtqmls1088a-mbls10xxa-mc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
10 #include <dt-bindings/net/ti-dp83867.h>
15 i2c-bus = <&sfp1_i2c>;
16 mod-def0-gpios = <&gpioexp2 2 GPIO_ACTIVE_LOW>;
17 los-gpios = <&gpioexp2 3 GPIO_ACTIVE_HIGH>;
18 tx-fault-gpios = <&gpioexp2 0 GPIO_ACTIVE_HIGH>;
19 tx-disable-gpios = <&gpioexp2 1 GPIO_ACTIVE_HIGH>;
24 i2c-bus = <&sfp2_i2c>;
[all …]
Dfsl-ls1028a-qds-13bb.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
9 * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
12 /dts-v1/;
16 #address-cells = <1>;
17 #size-cells = <0>;
19 slot1_sgmii: ethernet-phy@2 {
22 compatible = "ethernet-phy-ieee802.3-c45";
27 phy-handle = <&slot1_sgmii>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/
Dmarvell,mv88e6xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
22 - enum:
23 - marvell,mv88e6085
24 - marvell,mv88e6190
25 - marvell,mv88e6250
43 - items:
44 - const: marvell,turris-mox-mv88e6085
[all …]
/linux-6.12.1/drivers/net/phy/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # PHY Layer Configuration
12 PHYlink models the link between the PHY and MAC, allowing fixed
17 tristate "PHY Device support and infrastructure"
22 Ethernet controllers are usually attached to PHY
24 managing PHY devices.
35 Adds support for a set of LED trigger events per-PHY. Link
38 supported by the PHY and also a one common "link" trigger as a
39 logical-or of all the link speed ones.
41 <mii bus id>:<phy>:<speed>
[all …]
/linux-6.12.1/arch/arm64/boot/dts/microchip/
Dsparx5_pcb135_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
24 compatible = "gpio-leds";
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-385-clearfog-gtr-l8.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 #include "armada-385-clearfog-gtr.dtsi"
7 compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
11 sfp1: sfp-1 {
13 pinctrl-0 = <&cf_gtr_sfp1_pins>;
14 pinctrl-names = "default";
15 i2c-bus = <&i2c0>;
16 mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
17 tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
22 switch0: ethernet-switch@4 {
[all …]
Darmada-381-netgear-gs110emx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 /dts-v1/;
5 #include "armada-385.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
14 /* So that mvebu u-boot can update the MAC addresses */
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-0 = <&front_button_pins>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-j784s4-evm-quad-port-eth-exp1.dtso1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
4 * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the
11 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
14 /dts-v1/;
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/phy/phy-cadence.h>
19 #include <dt-bindings/phy/phy.h>
21 #include "k3-pinctrl.h"
22 #include "k3-serdes.h"
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Dcn9130-crb.dtsi1 // SPDX-License-Identifier: GPL-2.0+
8 #include <dt-bindings/gpio/gpio.h>
12 stdout-path = "serial0:115200n8";
29 ap0_reg_mmc_vccq: regulator-1 {
30 compatible = "regulator-gpio";
31 regulator-name = "ap0_mmc_vccq";
32 regulator-min-microvolt = <1800000>;
33 regulator-max-microvolt = <3300000>;
39 cp0_reg_usb3_vbus1: regulator-2 {
40 compatible = "regulator-fixed";
[all …]
Darmada-3720-turris-mox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
16 compatible = "cznic,turris-mox", "marvell,armada3720",
28 stdout-path = "serial0:115200n8";
37 compatible = "gpio-leds";
41 linux,default-trigger = "default-on";
[all …]

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