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/linux-6.12.1/drivers/gpu/drm/i915/gem/
Di915_gem_context_types.h34 * struct i915_gem_engines - A set of engines
38 /** @link: Link in i915_gem_context::stale::engines */
45 /** @fence: Fence used for delayed destruction of engines */
51 /** @num_engines: Number of engines in this set */
54 /** @engines: Array of engines */
55 struct intel_context *engines[]; member
62 /** @idx: Index into i915_gem_engines::engines */
65 /** @engines: Engine set being iterated */
66 const struct i915_gem_engines *engines; member
89 * This struct describes an engine that a context may contain. Engines
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Di915_gem_context.c396 struct i915_gem_proto_engine *engines; member
425 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_INVALID) { in set_proto_ctx_engines_balance()
452 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) { in set_proto_ctx_engines_balance()
470 set->engines[idx].type = I915_GEM_ENGINE_TYPE_PHYSICAL; in set_proto_ctx_engines_balance()
471 set->engines[idx].engine = siblings[0]; in set_proto_ctx_engines_balance()
474 set->engines[idx].type = I915_GEM_ENGINE_TYPE_BALANCED; in set_proto_ctx_engines_balance()
475 set->engines[idx].num_siblings = num_siblings; in set_proto_ctx_engines_balance()
476 set->engines[idx].siblings = siblings; in set_proto_ctx_engines_balance()
517 if (set->engines[idx].type == I915_GEM_ENGINE_TYPE_INVALID) { in set_proto_ctx_engines_bond()
522 if (set->engines[idx].type != I915_GEM_ENGINE_TYPE_PHYSICAL) { in set_proto_ctx_engines_bond()
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Di915_gem_context.h186 return rcu_dereference_protected(ctx->engines, in i915_gem_context_engines()
211 struct i915_gem_engines *e = rcu_dereference(ctx->engines); in i915_gem_context_get_engine()
214 else if (likely(idx < e->num_engines && e->engines[idx])) in i915_gem_context_get_engine()
215 ce = intel_context_get(e->engines[idx]); in i915_gem_context_get_engine()
225 struct i915_gem_engines *engines) in i915_gem_engines_iter_init() argument
227 it->engines = engines; in i915_gem_engines_iter_init()
234 #define for_each_gem_engine(ce, engines, it) \ argument
235 for (i915_gem_engines_iter_init(&(it), (engines)); \
/linux-6.12.1/drivers/gpu/drm/i915/gem/selftests/
Dmock_context.c32 INIT_LIST_HEAD(&ctx->stale.engines); in mock_context()
52 RCU_INIT_POINTER(ctx->engines, e); in mock_context()
113 struct i915_gem_engines *engines; in live_context_for_engine() local
118 engines = alloc_engines(1); in live_context_for_engine()
119 if (!engines) in live_context_for_engine()
124 __free_engines(engines, 0); in live_context_for_engine()
130 __free_engines(engines, 0); in live_context_for_engine()
135 engines->engines[0] = ce; in live_context_for_engine()
136 engines->num_engines = 1; in live_context_for_engine()
140 engines = rcu_replace_pointer(ctx->engines, engines, 1); in live_context_for_engine()
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/linux-6.12.1/drivers/crypto/marvell/octeontx2/
Dotx2_cptpf_ucode.h15 * On OcteonTX2 platform IPSec ucode can use both IE and SE engines therefore
16 * IE and SE engines can be attached to the same engine group.
26 /* Maximum number of supported engines/cores on OcteonTX2/CN10K platform */
94 /* Maximum and current number of engines available for all engine groups */
104 /* Engines reserved to an engine group */
107 int count; /* number of engines attached */
109 unsigned long *bmap; /* attached engines bitmap */
110 struct otx2_cpt_ucode *ucode; /* ucode used by these engines */
132 /* engines attached */
141 * when it has engines attached and ucode loaded
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/linux-6.12.1/drivers/platform/x86/
Dpcengines-apuv2.c4 * PC-Engines APUv2/APUv3 board platform driver
140 DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
149 DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
158 DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
159 DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
168 DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
177 DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
186 DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
187 DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu3")
195 DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
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/linux-6.12.1/drivers/gpu/drm/i915/gt/
Dselftest_rc6.c163 struct intel_engine_cs *engine, **engines; in randomised_engines() local
173 engines = kmalloc_array(n, sizeof(*engines), GFP_KERNEL); in randomised_engines()
174 if (!engines) in randomised_engines()
179 engines[n++] = engine; in randomised_engines()
181 i915_prandom_shuffle(engines, sizeof(*engines), n, prng); in randomised_engines()
184 return engines; in randomised_engines()
190 struct intel_engine_cs **engines; in live_rc6_ctx_wa() local
199 engines = randomised_engines(gt, &prng, &count); in live_rc6_ctx_wa()
200 if (!engines) in live_rc6_ctx_wa()
204 struct intel_engine_cs *engine = engines[n]; in live_rc6_ctx_wa()
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Dintel_engine_user.c82 struct list_head *engines) in sort_engines() argument
89 list_add(&engine->uabi_list, engines); in sort_engines()
91 list_sort(NULL, engines, engine_cmp); in sort_engines()
111 for_each_uabi_engine(engine, i915) { /* all engines must agree! */ in set_scheduler_caps()
210 LIST_HEAD(engines); in intel_engines_driver_register()
212 sort_engines(i915, &engines); in intel_engines_driver_register()
216 list_for_each_safe(it, next, &engines) { in intel_engines_driver_register()
221 continue; /* ignore incomplete engines */ in intel_engines_driver_register()
/linux-6.12.1/drivers/crypto/marvell/octeontx/
Dotx_cptpf_ucode.h22 * On OcteonTX 83xx platform, only one type of engines is allowed to be
39 /* Maximum number of supported engines/cores on OcteonTX 83XX platform */
101 /* Maximum and current number of engines available for all engine groups */
109 /* Engines reserved to an engine group */
112 int count; /* number of engines attached */
114 unsigned long *bmap; /* attached engines bitmap */
115 struct otx_cpt_ucode *ucode; /* ucode used by these engines */
138 /* engines attached */
149 * when it has engines attached and ucode loaded
159 int engs_num; /* total number of engines supported */
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/linux-6.12.1/drivers/net/ethernet/packetengines/
DKconfig3 # Packet Engines device configuration
7 bool "Packet Engines devices"
15 the questions about Packet Engines devices. If you say Y, you will
21 tristate "Packet Engines Hamachi GNIC-II support"
31 tristate "Packet Engines Yellowfin Gigabit-NIC support"
35 Say Y here if you have a Packet Engines G-NIC PCI Gigabit Ethernet
/linux-6.12.1/Documentation/devicetree/bindings/fsi/
Dfsi.txt5 engines within those slaves. However, we have a facility to match devicetree
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
16 represent the FSI slaves and their slave engines. As a basic outline:
41 adding subordinate device tree nodes as children of FSI engines.
79 Each slave provides an address-space, under which the engines are accessible.
91 FSI engines (devices)
94 Engines are identified by their address under the slaves' address spaces. We
116 additional engines, but they don't necessarily need to be describe in the
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_gt.h38 * xe_gt_record_user_engines - save data related to engines available to
42 * Walk the available HW engines from gt->info.engine_mask and calculate data
43 * related to those engines that may be used by userspace. To be used whenever
44 * available engines change in runtime (e.g. with ccs_mode) or during
58 * xe_gt_any_hw_engine_by_reset_domain - scan the list of engines and return the
67 * xe_gt_any_hw_engine - scan the list of engines and return the
Dxe_gt_ccs_mode.c33 * assignment of compute slices to compute engines would be, in __xe_gt_apply_ccs_mode()
38 * With 2 engines (ccs0, ccs1): in __xe_gt_apply_ccs_mode()
42 * With 4 engines (ccs0, ccs1, ccs2, ccs3): in __xe_gt_apply_ccs_mode()
131 * Ensure number of engines specified is valid and there is an in ccs_mode_store()
132 * exact multiple of engines for slices. in ccs_mode_store()
136 xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n", in ccs_mode_store()
181 * number of compute hardware engines to which the available compute slices
Dxe_query.c192 struct drm_xe_query_engines *engines; in query_engines() local
206 engines = kzalloc(size, GFP_KERNEL); in query_engines()
207 if (!engines) in query_engines()
215 engines->engines[i].instance.engine_class = in query_engines()
217 engines->engines[i].instance.engine_instance = in query_engines()
219 engines->engines[i].instance.gt_id = gt->info.id; in query_engines()
224 engines->num_engines = i; in query_engines()
226 if (copy_to_user(query_ptr, engines, size)) { in query_engines()
227 kfree(engines); in query_engines()
230 kfree(engines); in query_engines()
Dxe_gt_types.h105 * the hardware engines, programmable execution units, and GuC. Each GT has
124 * @info.engine_mask: mask of engines present on GT. Some of
214 * @ccs_mode: Number of compute engines enabled.
215 * Allows fixed mapping of available compute slices to compute engines.
326 /** @hw_engines: hardware engines on the GT */
414 /** @user_engines: engines present in GT and available to userspace */
418 * consideration only engines available to userspace
424 * number of engines available to userspace
/linux-6.12.1/Documentation/netlabel/
Dintroduction.rst15 is composed of three main components, the protocol engines, the communication
18 Protocol Engines
21 The protocol engines are responsible for both applying and retrieving the
25 refrain from calling the protocol engines directly, instead they should use
45 independent interface to the underlying NetLabel protocol engines. In addition
/linux-6.12.1/drivers/gpu/drm/xe/tests/
Dxe_pci_test.c22 /* RCS, CCS, and BCS engines are allowed on the graphics IP */ in check_graphics_ip()
27 /* Any remaining engines are an error */ in check_graphics_ip()
36 /* VCS, VECS and GSCCS engines are allowed on the media IP */ in check_media_ip()
41 /* Any remaining engines are an error */ in check_media_ip()
/linux-6.12.1/drivers/crypto/marvell/cesa/
Dcesa.c377 struct mv_cesa_engine *engine = &cesa->engines[idx]; in mv_cesa_get_sram()
422 struct mv_cesa_engine *engine = &cesa->engines[idx]; in mv_cesa_put_sram()
439 struct mv_cesa_engine *engines; in mv_cesa_probe() local
470 cesa->engines = devm_kcalloc(dev, caps->nengines, sizeof(*engines), in mv_cesa_probe()
472 if (!cesa->engines) in mv_cesa_probe()
490 struct mv_cesa_engine *engine = &cesa->engines[i]; in mv_cesa_probe()
574 clk_disable_unprepare(cesa->engines[i].zclk); in mv_cesa_probe()
575 clk_disable_unprepare(cesa->engines[i].clk); in mv_cesa_probe()
577 if (cesa->engines[i].irq > 0) in mv_cesa_probe()
578 irq_set_affinity_hint(cesa->engines[i].irq, NULL); in mv_cesa_probe()
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/linux-6.12.1/tools/include/uapi/drm/
Di915_drm.h160 * Different engines serve different roles, and there may be more than one
163 * on a certain subset of engines, or for providing information about that
170 * Render engines support instructions used for 3D, Compute (GPGPU),
181 * Copy engines (also referred to as "blitters") support instructions
184 * Copy engines can perform pre-defined logical or bitwise operations
192 * Video engines (also referred to as "bit stream decode" (BSD) or
201 * Video enhancement engines (also referred to as "vebox") support
209 * Compute engines support a subset of the instructions available
210 * on render engines: compute engines support Compute (GPGPU) and
728 * value reports the support of context isolation for individual engines by
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/linux-6.12.1/include/uapi/drm/
Di915_drm.h160 * Different engines serve different roles, and there may be more than one
163 * on a certain subset of engines, or for providing information about that
170 * Render engines support instructions used for 3D, Compute (GPGPU),
181 * Copy engines (also referred to as "blitters") support instructions
184 * Copy engines can perform pre-defined logical or bitwise operations
192 * Video engines (also referred to as "bit stream decode" (BSD) or
201 * Video enhancement engines (also referred to as "vebox") support
209 * Compute engines support a subset of the instructions available
210 * on render engines: compute engines support Compute (GPGPU) and
728 * value reports the support of context isolation for individual engines by
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Dxe_drm.h56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │
260 * struct drm_xe_query_engines - describe engines
267 /** @num_engines: number of engines returned in @engines */
271 /** @engines: The returned engines for this device */
272 struct drm_xe_engine engines[]; member
446 * drm_xe_query_mem_regions that are nearest to the current engines
456 * drm_xe_query_mem_regions that are far from the engines of this GT.
657 * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
661 * struct drm_xe_query_engines *engines;
669 * engines = malloc(query.size);
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/linux-6.12.1/drivers/gpu/drm/i915/gt/uc/
Dselftest_guc_multi_lrc.c13 static void logical_sort(struct intel_engine_cs **engines, int num_engines) in logical_sort() argument
20 if (engines[j]->logical_mask & BIT(i)) { in logical_sort()
21 sorted[i] = engines[j]; in logical_sort()
26 memcpy(*engines, *sorted, in logical_sort()
122 gt_dbg(gt, "Not enough engines in class: %d\n", class); in __intel_guc_multi_lrc_basic()
/linux-6.12.1/drivers/leds/
Dleds-apu.c86 /* PC Engines APU with factory bios "SageBios_PCEngines_APU-45" */
90 DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
94 /* PC Engines APU with "Mainline" bios >= 4.6.8 */
98 DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
185 pr_err("No PC Engines APUv1 board detected. For APUv2,3 support, enable CONFIG_PCENGINES_APU2\n"); in apu_led_init()
219 MODULE_DESCRIPTION("PC Engines APU1 front LED driver");
/linux-6.12.1/Documentation/devicetree/bindings/crypto/
Daspeed,ast2600-acry.yaml7 title: ASPEED ACRY ECDSA/RSA Hardware Accelerator Engines
13 The ACRY ECDSA/RSA engines is designed to accelerate the throughput
15 divided into two independent engines - ECC Engine and RSA Engine.
/linux-6.12.1/Documentation/misc-devices/
Dmrvl_cn10k_dpi.rst12 mailbox logic, and a set of DMA engines & DMA command queues.
20 the DMA engines and VF device's DMA command queues. Also, driver creates
38 a pem port to which DMA engines are wired.

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