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/linux-6.12.1/arch/arm64/boot/dts/cavium/
Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
58 method = "smc";
62 #address-cells = <2>;
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/linux-6.12.1/Documentation/firmware-guide/acpi/
Dmethod-tracing.rst1 .. SPDX-License-Identifier: GPL-2.0
15 method tracing facility.
20 ACPICA provides method tracing capability. And two functions are
24 -----------
28 ACPI_DEBUG_PRINT() macro can be reduced at 2 levels - per-component
30 /sys/module/acpi/parameters/debug_layer) and per-type level (known as
33 But when the particular layer/level is applied to the control method
36 to only enable the particular debug layer/level (normally more detailed)
37 logs when the control method evaluation is started, and disable the
38 detailed logging when the control method evaluation is stopped.
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/linux-6.12.1/arch/arm64/boot/dts/amd/
Delba-16core.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu-map {
44 compatible = "arm,cortex-a72";
46 next-level-cache = <&l2_0>;
47 enable-method = "psci";
52 compatible = "arm,cortex-a72";
54 next-level-cache = <&l2_0>;
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/linux-6.12.1/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
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/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-ap810-ap0-octa-core.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap810-ap0.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 compatible = "marvell,armada-ap810-octa";
18 compatible = "arm,cortex-a72";
20 enable-method = "psci";
24 compatible = "arm,cortex-a72";
26 enable-method = "psci";
30 compatible = "arm,cortex-a72";
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/linux-6.12.1/arch/arm/kernel/
Dcpuidle.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 * arm_cpuidle_simple_enter() - a wrapper to cpu_do_idle()
37 * arm_cpuidle_suspend() - function to enter low power idle states
53 * arm_cpuidle_get_ops() - find a registered cpuidle_ops by name
54 * @method: the method name
57 * method name.
61 static const struct cpuidle_ops *__init arm_cpuidle_get_ops(const char *method) in arm_cpuidle_get_ops() argument
65 for (; m->method; m++) in arm_cpuidle_get_ops()
66 if (!strcmp(m->method, method)) in arm_cpuidle_get_ops()
67 return m->ops; in arm_cpuidle_get_ops()
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/linux-6.12.1/arch/arm64/boot/dts/hisilicon/
Dhip05.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
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Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
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/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt6755.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&sysirq>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
18 method = "smc";
22 #address-cells = <1>;
23 #size-cells = <0>;
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/linux-6.12.1/arch/arm64/kernel/
Dcpu_ops.c1 // SPDX-License-Identifier: GPL-2.0-only
46 if (!strcmp(name, (*ops)->name)) in cpu_get_ops()
68 enable_method = of_get_property(dn, "enable-method", NULL); in cpu_read_enable_method()
71 * The boot CPU may not have an enable method (e.g. in cpu_read_enable_method()
72 * when spin-table is used for secondaries). in cpu_read_enable_method()
76 pr_err("%pOF: missing enable-method property\n", in cpu_read_enable_method()
85 * checking the enable method since for some in cpu_read_enable_method()
90 pr_err("Unsupported ACPI enable-method\n"); in cpu_read_enable_method()
97 * Read a cpu's enable method and record it in cpu_ops.
104 return -ENODEV; in init_cpu_ops()
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/linux-6.12.1/Documentation/devicetree/bindings/
Dnuma.txt6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
44 - distance-matrix
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/linux-6.12.1/arch/arm64/boot/dts/arm/
Dfoundation-v8-psci.dtsi9 compatible = "arm,psci-1.0";
10 method = "smc";
15 enable-method = "psci";
19 enable-method = "psci";
23 enable-method = "psci";
27 enable-method = "psci";
Dfoundation-v8-spin-table.dtsi8 enable-method = "spin-table";
9 cpu-release-addr = <0x0 0x8000fff8>;
13 enable-method = "spin-table";
14 cpu-release-addr = <0x0 0x8000fff8>;
18 enable-method = "spin-table";
19 cpu-release-addr = <0x0 0x8000fff8>;
23 enable-method = "spin-table";
24 cpu-release-addr = <0x0 0x8000fff8>;
/linux-6.12.1/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dmarvell,berlin-smp2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
5 This document describes the "al,alpine-smp" method for
7 "al,alpine-smp" enable method should be defined in the
10 Enable method name: "al,alpine-smp"
12 Compatible CPUs: "arm,cortex-a15"
16 This enable method requires valid nodes compatible with
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
26 - compatible : Should contain "al,alpine-cpu-resume".
27 - reg : Offset and length of the register set for the device
33 #address-cells = <1>;
[all …]
Dnuvoton,npcm750-smp2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
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/linux-6.12.1/arch/arm64/boot/dts/amazon/
Dalpine-v3.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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/linux-6.12.1/Documentation/PCI/
Dpci-iov-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Yu Zhao <yu.zhao@intel.com>
10 - Donald Dutile <ddutile@redhat.com>
15 What is SR-IOV
16 --------------
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
34 How can I enable SR-IOV capability
35 ----------------------------------
37 Multiple methods are available for SR-IOV enablement.
38 In the first method, the device driver (PF driver) will control the
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/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Damlogic-t7.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/amlogic,t7-pwrc.h>
8 #include "amlogic-t7-reset.h"
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <0x2>;
17 #size-cells = <0x0>;
19 cpu-map {
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/linux-6.12.1/arch/arm64/boot/dts/exynos/
Dexynosautov920.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h>
15 #address-cells = <2>;
16 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a78-pmu";
37 compatible = "fixed-clock";
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/linux-6.12.1/arch/arm/boot/dts/qcom/
Dqcom-msm8916-smp.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 enable-method = "qcom,msm8916-smp";
9 enable-method = "qcom,msm8916-smp";
12 enable-method = "qcom,msm8916-smp";
15 enable-method = "qcom,msm8916-smp";
18 idle-states {
19 /delete-property/ entry-method;
29 compatible = "qcom,idle-state-spc", "arm,idle-state";
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Ds32g3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright 2021-2024 NXP
7 * Andra-Teodora Ilie <andra.ilie@nxp.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <0x02>;
16 #size-cells = <0x02>;
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cpu-map {
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/linux-6.12.1/arch/sh/boards/
Dof-generic.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
59 const char *method = NULL; in sh_of_smp_probe() local
70 if (!method) in sh_of_smp_probe()
71 of_property_read_string(np, "enable-method", &method); in sh_of_smp_probe()
78 if (!method) { in sh_of_smp_probe()
80 of_property_read_string(np, "enable-method", &method); in sh_of_smp_probe()
84 pr_info("CPU enable method: %s\n", method); in sh_of_smp_probe()
85 if (method) in sh_of_smp_probe()
86 for (; m->method; m++) in sh_of_smp_probe()
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/linux-6.12.1/arch/arm64/boot/dts/sprd/
Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra210-p2530.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 stdout-path = "serial0:115200n8";
24 /delete-property/ dmas;
25 /delete-property/ dma-names;
31 clock-frequency = <400000>;
35 nvidia,invert-interrupt;
41 bus-width = <8>;
42 non-removable;
45 clk32k_in: clock-32k {
46 compatible = "fixed-clock";
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