| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | intel,lgm-emmc-phy.yaml | 4 $id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
7 title: Intel Lightning Mountain(LGM) eMMC PHY
13 Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
14 node is used to reference the base address of eMMC phy registers.
16 The eMMC PHY node should be the child of a syscon node with the
27 - intel,lgm-emmc-phy
28 - intel,keembay-emmc-phy
59 emmc_phy: emmc-phy@a8 {
60 compatible = "intel,lgm-emmc-phy";
62 clocks = <&emmc>;
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| /linux-6.12.1/Documentation/devicetree/bindings/mmc/ |
| D | allwinner,sun4i-a10-mmc.yaml | 25 - const: allwinner,sun8i-a83t-emmc
28 - const: allwinner,sun50i-a64-emmc
30 - const: allwinner,sun50i-a100-emmc
36 - const: allwinner,sun8i-r40-emmc
37 - const: allwinner,sun50i-a64-emmc
42 - const: allwinner,sun50i-h5-emmc
43 - const: allwinner,sun50i-a64-emmc
48 - const: allwinner,sun50i-h6-emmc
49 - const: allwinner,sun50i-a64-emmc
54 - const: allwinner,sun20i-d1-emmc
[all …]
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| D | mmc-pwrseq-emmc.yaml | 4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml#
7 title: Simple eMMC hardware reset provider
13 The purpose of this driver is to perform standard eMMC hw reset
16 fix possible issues if bootloader has left eMMC card in initialized or
19 doesn't have hardware reset logic connected to emmc card and (limited or
20 broken) ROM bootloaders are unable to read second stage from the emmc
25 const: mmc-pwrseq-emmc
31 and then deasserted to perform eMMC card reset. To perform
45 compatible = "mmc-pwrseq-emmc";
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| D | marvell,xenon-sdhci.yaml | 76 - emmc 5.1 phy
77 - emmc 5.0 phy
79 Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
80 marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
81 choice if this property is not provided. To select eMMC 5.0 PHY, set:
82 marvell,xenon-phy-type = "emmc 5.0 phy"
84 All those types of PHYs can support eMMC, SD and SDIO. Please note that
86 entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
87 that this Xenon SDHC only supports eMMC 5.1.
96 Only available for eMMC PHY.
[all …]
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| D | mmc-controller.yaml | 50 Non-removable slot (like eMMC); assume always present.
93 - for eMMC, the maximum supported frequency is 200MHz,
112 line. Not used in combination with eMMC or SDIO.
173 eMMC hardware reset is supported
193 eMMC high-speed DDR mode (1.2V I/O) is supported.
198 eMMC high-speed DDR mode (1.8V I/O) is supported.
203 eMMC high-speed DDR mode (3.3V I/O) is supported.
208 eMMC HS200 mode (1.2V I/O) is supported.
213 eMMC HS200 mode (1.8V I/O) is supported.
218 eMMC HS400 mode (1.2V I/O) is supported.
[all …]
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| /linux-6.12.1/Documentation/driver-api/mmc/ |
| D | mmc-tools.rst | 16 - Determine the eMMC writeprotect status.
17 - Set the eMMC writeprotect status.
18 - Set the eMMC data sector size to 4KB by disabling emulation.
25 - Enable the eMMC BKOPS feature.
26 - Permanently enable the eMMC H/W Reset feature.
27 - Permanently disable the eMMC H/W Reset feature.
33 - Enable the eMMC cache feature.
34 - Disable the eMMC cache feature.
|
| /linux-6.12.1/arch/arm64/boot/dts/amlogic/ |
| D | meson-gxl-s905x-libretech-cc.dts | 46 emmc_pwrseq: emmc-pwrseq {
47 compatible = "mmc-pwrseq-emmc";
127 /* This is provided by LDOs on the eMMC daugther card */
272 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
273 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
274 "eMMC Clk", "eMMC Reset", "eMMC CMD",
275 "ALT BOOT MODE", "", "", "", "eMMC Data Strobe",
323 /* eMMC */
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| D | meson-gxl-s905x-khadas-vim.dts | 184 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
185 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
186 "eMMC Clk", "eMMC Reset", "eMMC CMD",
187 "", "BOOT_MODE", "", "", "eMMC Data Strobe",
|
| D | meson-gxl-s805x-libretech-ac.dts | 53 emmc_pwrseq: emmc-pwrseq {
54 compatible = "mmc-pwrseq-emmc";
249 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3",
250 "eMMC D4", "eMMC D5", "eMMC D6", "eMMC D7",
251 "eMMC Clk", "eMMC Reset", "eMMC CMD",
280 /* eMMC */
|
| D | meson-gxbb-odroidc2.dts | 161 emmc_pwrseq: emmc-pwrseq {
162 compatible = "mmc-pwrseq-emmc";
302 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
303 "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
304 "eMMC Reset", "eMMC CMD",
364 /* eMMC */
|
| D | meson-gxbb-nanopi-k2.dts | 107 emmc_pwrseq: emmc-pwrseq {
108 compatible = "mmc-pwrseq-emmc";
260 "eMMC D0", "eMMC D1", "eMMC D2", "eMMC D3", "eMMC D4",
261 "eMMC D5", "eMMC D6", "eMMC D7", "eMMC Clk",
262 "eMMC Reset", "eMMC CMD",
263 "", "", "", "", "eMMC DS",
362 /* eMMC */
|
| /linux-6.12.1/arch/arm/boot/dts/nxp/imx/ |
| D | Makefile | 73 imx6dl-cubox-i-emmc-som-v15.dtb \
94 imx6dl-hummingboard-emmc-som-v15.dtb \
97 imx6dl-hummingboard2-emmc-som-v15.dtb \
168 imx6q-cubox-i-emmc-som-v15.dtb \
201 imx6q-hummingboard-emmc-som-v15.dtb \
204 imx6q-hummingboard2-emmc-som-v15.dtb \
222 imx6q-phytec-mira-rdk-emmc.dtb \
310 imx6ul-isiot-emmc.dtb \
322 imx6ul-phytec-segin-ff-rdk-emmc.dtb \
330 imx6ull-colibri-emmc-aster.dtb \
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| D | imx6ull-colibri-emmc-eval-v3.dts | 8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3";
13 compatible = "toradex,colibri-imx6ull-emmc-eval",
14 "toradex,colibri-imx6ull-emmc",
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| D | imx6ull-colibri-emmc-iris.dts | 8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Iris";
13 compatible = "toradex,colibri-imx6ull-emmc-iris",
14 "toradex,colibri-imx6ull-emmc",
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| D | imx6ull-colibri-emmc-aster.dts | 8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Aster";
13 compatible = "toradex,colibri-imx6ull-emmc-aster",
14 "toradex,colibri-imx6ull-emmc",
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| D | imx6ull-colibri-emmc-iris-v2.dts | 8 #include "imx6ull-colibri-emmc-nonwifi.dtsi"
12 model = "Toradex Colibri iMX6ULL 1G (eMMC) on Colibri Iris V2";
13 compatible = "toradex,colibri-imx6ull-emmc-iris-v2",
14 "toradex,colibri-imx6ull-emmc",
|
| D | imx7d-colibri-emmc-aster.dts | 8 #include "imx7d-colibri-emmc.dtsi"
12 model = "Toradex Colibri iMX7D 1GB (eMMC) on Aster Carrier Board";
13 compatible = "toradex,colibri-imx7d-emmc-aster",
14 "toradex,colibri-imx7d-emmc",
|
| D | imx7d-colibri-emmc-eval-v3.dts | 7 #include "imx7d-colibri-emmc.dtsi"
11 model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3";
12 compatible = "toradex,colibri-imx7d-emmc-eval-v3",
13 "toradex,colibri-imx7d-emmc",
|
| /linux-6.12.1/arch/arm/boot/dts/allwinner/ |
| D | sun7i-a20-olimex-som-evb-emmc.dts | 3 * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
14 model = "Olimex A20-Olimex-SOM-EVB-eMMC";
15 compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
18 compatible = "mmc-pwrseq-emmc";
30 emmc: emmc@0 { label
|
| D | sun7i-a20-olimex-som204-evb-emmc.dts | 3 * Device Tree Source for A20-SOM204-EVB-eMMC Board
13 model = "Olimex A20-SOM204-EVB-eMMC";
14 compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
17 compatible = "mmc-pwrseq-emmc";
29 emmc: emmc@0 { label
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| D | sun7i-a20-olinuxino-lime-emmc.dts | 10 model = "Olimex A20-OLinuXino-LIME-eMMC";
11 compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20";
14 compatible = "mmc-pwrseq-emmc";
27 emmc: emmc@0 { label
|
| /linux-6.12.1/arch/arm/boot/dts/amlogic/ |
| D | meson8b-ec100.dts | 30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
423 "NAND_D0 (EMMC)", "NAND_D1 (EMMC)",
424 "NAND_D2 (EMMC)", "NAND_D3 (EMMC)",
425 "NAND_D4 (EMMC)", "NAND_D5 (EMMC)",
426 "NAND_D6 (EMMC)", "NAND_D7 (EMMC)",
427 "NAND_CS1 (EMMC)", "NAND_CS2 iNAND_RS1 (EMMC)",
428 "NAND_nR/B iNAND_CMD (EMMC)", "NAND_ALE (EMMC)",
429 "NAND_CLE (EMMC)", "nRE_S1 NAND_nRE (EMMC)",
430 "nWE_S1 NAND_nWE (EMMC)", "", "", "SPI_CS",
|
| D | meson8b-odroidc1.dts | 30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
262 "SDC_D0 (EMMC)", "SDC_D1 (EMMC)",
263 "SDC_D2 (EMMC)", "SDC_D3 (EMMC)",
264 "SDC_D4 (EMMC)", "SDC_D5 (EMMC)",
265 "SDC_D6 (EMMC)", "SDC_D7 (EMMC)",
266 "SDC_CLK (EMMC)", "SDC_RSTn (EMMC)",
267 "SDC_CMD (EMMC)", "BOOT_SEL", "", "", "",
|
| /linux-6.12.1/Documentation/devicetree/bindings/soc/intel/ |
| D | intel,lgm-syscon.yaml | 31 "^emmc-phy@[0-9a-f]+$":
32 $ref: /schemas/phy/intel,lgm-emmc-phy.yaml#
51 emmc-phy@a8 {
52 compatible = "intel,lgm-emmc-phy";
54 clocks = <&emmc>;
|
| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3368-evb.dtsi | 13 mmc0 = &emmc;
67 emmc_pwrseq: emmc-pwrseq {
68 compatible = "mmc-pwrseq-emmc";
120 &emmc {
165 emmc {
166 emmc_bus8: emmc-bus8 {
177 emmc-clk {
181 emmc-cmd {
185 emmc_reset: emmc-reset {
|