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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra20-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
17 various performance-affecting settings beyond the obvious SDRAM configuration
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/linux-6.12.1/drivers/memory/tegra/
Dtegra210-emc-table.c1 // SPDX-License-Identifier: GPL-2.0
8 #include "tegra210-emc.h"
15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local
19 timings = memremap(rmem->base, rmem->size, MEMREMAP_WB); in tegra210_emc_table_device_init()
21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init()
22 return -ENOMEM; in tegra210_emc_table_device_init()
32 /* only the nominal and derated tables are expected */ in tegra210_emc_table_device_init()
33 if (emc->derated) { in tegra210_emc_table_device_init()
34 dev_warn(dev, "excess EMC table '%s'\n", rmem->name); in tegra210_emc_table_device_init()
38 if (emc->nominal) { in tegra210_emc_table_device_init()
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Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
216 * There are multiple sources in the EMC driver which could request
221 /* protect shared rate-change code path */
237 struct tegra_emc *emc = data; in tegra_emc_isr() local
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
256 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
262 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
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Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
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/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-firmware-efi24 Contact: linux-efi@vger.kernel.org
26 Tables found via the EFI System Table. The order in
27 which the tables are printed forms an ABI and newer
32 What: /sys/firmware/efi/tables/rci2
34 Contact: Narendra K <Narendra.K@dell.com>, linux-bugs@dell.com
36 Table version 2 on Dell EMC PowerEdge systems in binary format
37 Users: It is used by Dell EMC OpenManage Server Administrator tool to
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
32 * pre-existing /chosen node to be available to insert the
41 reserved-memory {
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Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
25 stdout-path = "serial0:115200n8";
44 vdd-supply = <&hdmi_vdd_reg>;
45 pll-supply = <&hdmi_pll_reg>;
47 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
33 * pre-existing /chosen node to be available to insert the
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/linux-6.12.1/drivers/firmware/efi/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 resource, and set aside for direct-access (device-dax) by
45 device-dax kmem facility. Say N to have the kernel treat this
88 calls. For compatibility with non-EFI loaders, the payload can be
90 loader implements the decompression algorithm and that non-EFI boot
135 bool "Add support for Quark capsules with non-standard headers"
194 Table version 2 on Dell EMC PowerEdge systems as a binary
195 attribute 'rci2' under /sys/firmware/efi/tables directory.
198 BIOS setup page in Dell EMC OpenManage Server Administrator tool.
201 Say Y here for Dell EMC PowerEdge systems.
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/linux-6.12.1/drivers/cpufreq/
Dtegra194-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved
8 #include <linux/dma-mapping.h>
19 #include <soc/tegra/bpmp-abi.h>
32 #define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu))
36 (data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base))
91 dev = get_cpu_device(policy->cpu); in tegra_cpufreq_set_bw()
93 return -ENODEV; in tegra_cpufreq_set_bw()
101 data->icc_dram_bw_scaling = false; in tegra_cpufreq_set_bw()
128 *ndiv = readl(data->cpu_data[cpu].freq_core_reg) & NDIV_MASK; in tegra234_get_cpu_ndiv()
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/linux-6.12.1/drivers/scsi/bnx2i/
Dbnx2i_hwi.c3 * Copyright (c) 2006 - 2013 Broadcom Corporation
14 * Maintained by: QLogic-Storage-Upstream@qlogic.com
25 * bnx2i_get_cid_num - get cid from ep
34 if (test_bit(BNX2I_NX2_DEV_57710, &ep->hba->cnic_dev_type)) in bnx2i_get_cid_num()
35 cid = ep->ep_cid; in bnx2i_get_cid_num()
37 cid = GET_CID_NUM(ep->ep_cid); in bnx2i_get_cid_num()
43 * bnx2i_adjust_qp_size - Adjust SQ/RQ/CQ size for 57710 device type
52 if (test_bit(BNX2I_NX2_DEV_5706, &hba->cnic_dev_type) || in bnx2i_adjust_qp_size()
53 test_bit(BNX2I_NX2_DEV_5708, &hba->cnic_dev_type) || in bnx2i_adjust_qp_size()
54 test_bit(BNX2I_NX2_DEV_5709, &hba->cnic_dev_type)) { in bnx2i_adjust_qp_size()
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