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/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra30-asus-tf300t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300t-init-hog {
13 gpio-hog;
15 output-low;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
7 #include <dt-bindings/clock/tegra124-car.h>
11 emc-timings-1 {
12 nvidia,ram-code = <1>;
14 timing-12750000 {
15 clock-frequency = <12750000>;
16 nvidia,parent-clock-frequency = <408000000>;
18 clock-names = "emc-parent";
21 timing-20400000 {
[all …]
Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300tg-init-hog {
13 gpio-hog;
16 <TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>,
25 <TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>,
28 output-low;
39 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
Dtegra30-asus-tf700t.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
20 remote-endpoint = <&bridge_input>;
21 bus-width = <24>;
36 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
44 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
52 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
60 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
68 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
Dtegra30-asus-tf201.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
19 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
27 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
43 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
51 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
57 /* Azurewave AW-NH615 BCM4329B1 */
[all …]
Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-3 {
8 nvidia,ram-code = <3>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
Dtegra30-lg-p880.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
16 pinctrl-names = "default";
17 pinctrl-0 = <&state_default>;
21 host-wlan-wake {
26 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
29 /* GNSS UART-B pinmux */
30 uartb-rxd {
35 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
Dtegra30-lg-p895.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-lg-x3.dtsi"
11 pinctrl-names = "default";
12 pinctrl-0 = <&state_default>;
15 /* GNSS UART-B pinmux */
16 uartb-cts-rxd {
22 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
24 uartb-rts-txd {
30 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
[all …]
Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
[all …]
Dtegra124-nyan-big-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra124-car.h>
7 emc-timings-1 {
8 nvidia,ram-code = <1>;
10 timing-12750000 {
11 clock-frequency = <12750000>;
12 nvidia,parent-clock-frequency = <408000000>;
14 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
Dtegra30-asus-nexus7-grouper-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
8 timing-25500000 {
9 clock-frequency = <25500000>;
11 nvidia,emem-configuration = <
33 timing-51000000 {
34 clock-frequency = <51000000>;
36 nvidia,emem-configuration = <
[all …]
Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
12 memory-controller@7000f400 {
13 emc-timings-0 {
14 timing-667000000 {
15 clock-frequency = <667000000>;
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
[all …]
Dtegra30-ouya.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
26 stdout-path = "serial0:115200n8";
30 trusted-foundations {
31 compatible = "tlm,trusted-foundations";
[all …]
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
32 * pre-existing /chosen node to be available to insert the
41 reserved-memory {
[all …]
Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
33 * pre-existing /chosen node to be available to insert the
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
[all …]
Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
22 maxItems: 1
26 - description: external memory clock
[all …]
/linux-6.12.1/drivers/memory/tegra/
Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
162 ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
172 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
203 (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
204 #define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)
210 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
[all …]
Dtegra20-emc.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/interconnect-provider.h>
96 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)
106 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)
112 #define EMC_FBIO_CFG5_DRAM_TYPE GENMASK(1, 0)
120 #define EMC_PWR_GATHER_CLEAR (1 << 8)
216 * There are multiple sources in the EMC driver which could request
221 /* protect shared rate-change code path */
237 struct tegra_emc *emc = data; in tegra_emc_isr() local
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
[all …]
Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
271 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
281 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
282 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
289 DRAM_TYPE_DDR1 = 1,
507 * There are multiple sources in the EMC driver which could request
512 /* protect shared rate-change code path */
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
[all …]
Dtegra210-emc-cc-r21021.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
20 #define INFO (1 << 0)
21 #define STEPS (1 << 1)
22 #define SUB_STEPS (1 << 2)
23 #define PRELOCK (1 << 3)
24 #define PRELOCK_STEPS (1 << 4)
25 #define ACTIVE_EN (1 << 5)
[all …]
/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/
Dlpc4350-hitex-eval.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "gpio-keys-polled";
43 poll-interval = <100>;
97 compatible = "gpio-leds";
102 linux,default-trigger = "heartbeat";
[all …]
Dlpc4357-myd-lpc4357.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
5 * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
8 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
17 compatible = "myir,myd-lpc4357", "nxp,lpc4357";
20 stdout-path = "serial3:115200n8";
29 compatible = "gpio-leds";
30 pinctrl-names = "default";
31 pinctrl-0 = <&led_pins>;
[all …]
Dlpc4357-ea4357-devkit.dts9 * Released under the terms of 3-clause BSD License
13 /dts-v1/;
18 #include "dt-bindings/input/input.h"
19 #include "dt-bindings/gpio/gpio.h"
23 compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
33 stdout-path = &uart0;
42 compatible = "regulator-fixed";
43 regulator-name = "3v3-supply";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
[all …]

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