| /linux-6.12.1/drivers/nvmem/ |
| D | sprd-efuse.c | 39 * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse,
40 * and we can only access the normal efuse in kernel. So define the normal
52 * when reading or writing data to efuse memory, the controller can save double
80 * efuse controller, so we need one hardware spinlock to synchronize between
83 static int sprd_efuse_lock(struct sprd_efuse *efuse) in sprd_efuse_lock() argument
87 mutex_lock(&efuse->mutex); in sprd_efuse_lock()
89 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sprd_efuse_lock()
92 dev_err(efuse->dev, "timeout get the hwspinlock\n"); in sprd_efuse_lock()
93 mutex_unlock(&efuse->mutex); in sprd_efuse_lock()
100 static void sprd_efuse_unlock(struct sprd_efuse *efuse) in sprd_efuse_unlock() argument
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| D | meson-mx-efuse.c | 3 * Amlogic Meson6, Meson8 and Meson8b eFuse Driver
49 static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg, in meson_mx_efuse_mask_bits() argument
54 data = readl(efuse->base + reg); in meson_mx_efuse_mask_bits()
58 writel(data, efuse->base + reg); in meson_mx_efuse_mask_bits()
61 static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse) in meson_mx_efuse_hw_enable() argument
65 err = clk_prepare_enable(efuse->core_clk); in meson_mx_efuse_hw_enable()
69 /* power up the efuse */ in meson_mx_efuse_hw_enable()
70 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1, in meson_mx_efuse_hw_enable()
73 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4, in meson_mx_efuse_hw_enable()
79 static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse) in meson_mx_efuse_hw_disable() argument
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| D | sc27xx-efuse.c | 16 /* Efuse controller registers definition */
80 * efuse controller, so we need one hardware spinlock to synchronize between
83 static int sc27xx_efuse_lock(struct sc27xx_efuse *efuse) in sc27xx_efuse_lock() argument
87 mutex_lock(&efuse->mutex); in sc27xx_efuse_lock()
89 ret = hwspin_lock_timeout_raw(efuse->hwlock, in sc27xx_efuse_lock()
92 dev_err(efuse->dev, "timeout to get the hwspinlock\n"); in sc27xx_efuse_lock()
93 mutex_unlock(&efuse->mutex); in sc27xx_efuse_lock()
100 static void sc27xx_efuse_unlock(struct sc27xx_efuse *efuse) in sc27xx_efuse_unlock() argument
102 hwspin_unlock_raw(efuse->hwlock); in sc27xx_efuse_unlock()
103 mutex_unlock(&efuse->mutex); in sc27xx_efuse_unlock()
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| D | rockchip-efuse.c | 3 * Rockchip eFuse Driver
58 struct rockchip_efuse_chip *efuse = context; in rockchip_rk3288_efuse_read() local
62 ret = clk_prepare_enable(efuse->clk); in rockchip_rk3288_efuse_read()
64 dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); in rockchip_rk3288_efuse_read()
68 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
71 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
73 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
74 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
76 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
78 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
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| D | jz4780-efuse.c | 3 * JZ4780 EFUSE Memory Support driver
10 * Currently supports JZ4780 efuse which has 8K programmable bit.
11 * Efuse is separated into seven segments as below:
72 struct jz4780_efuse *efuse = context; in jz4780_efuse_read() local
87 regmap_update_bits(efuse->map, JZ_EFUCTRL, in jz4780_efuse_read()
94 ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE, in jz4780_efuse_read()
99 dev_err(efuse->dev, "Time out while reading efuse data"); in jz4780_efuse_read()
103 ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0), in jz4780_efuse_read()
119 .name = "jz4780-efuse",
142 struct jz4780_efuse *efuse; in jz4780_efuse_probe() local
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| D | Makefile | 28 nvmem_jz4780_efuse-y := jz4780-efuse.o
38 nvmem_meson_efuse-y := meson-efuse.o
40 nvmem_meson_mx_efuse-y := meson-mx-efuse.o
43 obj-$(CONFIG_NVMEM_MTK_EFUSE) += nvmem_mtk-efuse.o
44 nvmem_mtk-efuse-y := mtk-efuse.o
58 nvmem_rockchip_efuse-y := rockchip-efuse.o
61 obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o
62 nvmem-sc27xx-efuse-y := sc27xx-efuse.o
68 nvmem_sprd_efuse-y := sprd-efuse.o
78 obj-$(CONFIG_NVMEM_UNIPHIER_EFUSE) += nvmem-uniphier-efuse.o
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| D | zynqmp_nvmem.c | 32 * efuse access type
44 * @flag: 0 - represents efuse read and 1- represents efuse write
49 * read/write efuse memory.
64 struct xilinx_efuse *efuse; in zynqmp_efuse_access() local
98 efuse = dma_alloc_coherent(dev, sizeof(struct xilinx_efuse), in zynqmp_efuse_access()
100 if (!efuse) in zynqmp_efuse_access()
112 efuse->flag = EFUSE_WRITE; in zynqmp_efuse_access()
114 efuse->flag = EFUSE_READ; in zynqmp_efuse_access()
117 efuse->src = dma_buf; in zynqmp_efuse_access()
118 efuse->size = words; in zynqmp_efuse_access()
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| D | Kconfig | 32 tristate "Apple eFuse support"
105 tristate "JZ4780 EFUSE Memory Support"
111 Say Y here to include support for JZ4780 efuse memory found on
158 tristate "Amlogic Meson GX eFuse Support"
161 This is a driver to retrieve specific values from the eFuse found on
168 tristate "Amlogic Meson6/Meson8/Meson8b eFuse Support"
171 This is a driver to retrieve specific values from the eFuse found on
185 tristate "Mediatek SoCs EFUSE support"
193 will be called efuse-mtk.
260 tristate "Rockchip eFuse Support"
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| /linux-6.12.1/arch/arm/boot/dts/aspeed/ |
| D | aspeed-bmc-delta-ahe50dc.dts | 8 efuse##n { \
10 vout-supply = <&efuse##n>; \
15 #define EFUSE(hexaddr, num) \ macro
16 efuse@##hexaddr { \
21 efuse##num: vout { \
22 regulator-name = __stringify(efuse##num##-reg); \
166 EFUSE(10, 03);
167 EFUSE(11, 04);
168 EFUSE(12, 01);
169 EFUSE(13, 02);
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| /linux-6.12.1/Documentation/devicetree/bindings/nvmem/ |
| D | mediatek,efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/mediatek,efuse.yaml#
7 title: MediaTek efuse
10 MediaTek's efuse is used for storing calibration data, it can be accessed
23 pattern: "^efuse@[0-9a-f]+$"
29 - mediatek,mt7622-efuse
30 - mediatek,mt7623-efuse
31 - mediatek,mt7981-efuse
32 - mediatek,mt7986-efuse
33 - mediatek,mt7988-efuse
34 - mediatek,mt8173-efuse
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| D | rockchip-efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/rockchip-efuse.yaml#
7 title: Rockchip eFuse
19 - rockchip,rk3066a-efuse
20 - rockchip,rk3188-efuse
21 - rockchip,rk3228-efuse
22 - rockchip,rk3288-efuse
23 - rockchip,rk3328-efuse
24 - rockchip,rk3368-efuse
25 - rockchip,rk3399-efuse
28 - rockchip,rockchip-efuse
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| D | sc27xx-efuse.txt | 1 = Spreadtrum SC27XX PMIC eFuse device tree bindings =
5 "sprd,sc2720-efuse"
6 "sprd,sc2721-efuse"
7 "sprd,sc2723-efuse"
8 "sprd,sc2730-efuse"
9 "sprd,sc2731-efuse"
10 - reg: Specify the address offset of efuse controller.
14 Are child nodes of eFuse, bindings of which as described in
29 efuse@380 {
30 compatible = "sprd,sc2731-efuse";
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| D | amlogic,meson6-efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/amlogic,meson6-efuse.yaml#
7 title: Amlogic Meson6 eFuse
20 - amlogic,meson6-efuse
21 - amlogic,meson8-efuse
22 - amlogic,meson8b-efuse
43 efuse: efuse@0 {
44 compatible = "amlogic,meson6-efuse";
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| D | amlogic,meson-gxbb-efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/amlogic,meson-gxbb-efuse.yaml#
7 title: Amlogic Meson GX eFuse
19 - const: amlogic,meson-gxbb-efuse
21 - const: amlogic,meson-gx-efuse
22 - const: amlogic,meson-gxbb-efuse
43 efuse: efuse {
44 compatible = "amlogic,meson-gxbb-efuse";
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| D | ingenic,jz4780-efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/ingenic,jz4780-efuse.yaml#
7 title: Ingenic JZ EFUSE driver
18 - ingenic,jz4780-efuse
24 # Handle for the ahb for the efuse.
38 efuse@134100d0 {
39 compatible = "ingenic,jz4780-efuse";
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| D | sprd-efuse.txt | 1 = Spreadtrum eFuse device tree bindings =
4 - compatible: Should be "sprd,ums312-efuse".
5 - reg: Specify the address offset of efuse controller.
11 Are child nodes of eFuse, bindings of which as described in
16 ap_efuse: efuse@32240000 {
17 compatible = "sprd,ums312-efuse";
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| D | socionext,uniphier-efuse.yaml | 4 $id: http://devicetree.org/schemas/nvmem/socionext,uniphier-efuse.yaml#
7 title: Socionext UniPhier eFuse
19 const: socionext,uniphier-efuse
32 efuse@100 {
33 compatible = "socionext,uniphier-efuse";
37 efuse@200 {
38 compatible = "socionext,uniphier-efuse";
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| /linux-6.12.1/Documentation/devicetree/bindings/fuse/ |
| D | nvidia,tegra20-fuse.yaml | 17 - nvidia,tegra20-efuse
18 - nvidia,tegra30-efuse
19 - nvidia,tegra114-efuse
20 - nvidia,tegra124-efuse
21 - nvidia,tegra210-efuse
22 - nvidia,tegra186-efuse
23 - nvidia,tegra194-efuse
24 - nvidia,tegra234-efuse
27 - const: nvidia,tegra132-efuse
28 - const: nvidia,tegra124-efuse
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| /linux-6.12.1/Documentation/devicetree/bindings/regulator/ |
| D | ti-abb-regulator.txt | 35 efuse: (see Optional properties)
36 RBB enable efuse Mask: (See Optional properties)
37 FBB enable efuse Mask: (See Optional properties)
38 Vset value efuse Mask: (See Optional properties)
47 - "efuse-address" - Contains efuse base address used to pick up ABB info.
49 "efuse-address" is required for this.
55 efuse: Mandatory if 'efuse-address' register is defined. Provides offset
56 from efuse-address to pick up ABB characteristics. Set to 0 if
57 'efuse-address' is not defined.
58 RBB enable efuse Mask: Optional if 'efuse-address' register is defined.
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| /linux-6.12.1/drivers/phy/mediatek/ |
| D | phy-mtk-pcie.c | 36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
52 * @sw_efuse_supported: support software to load eFuse data
65 * @sw_efuse_en: software eFuse enable status
67 * @efuse: pointer to eFuse data for each lane
77 struct mtk_pcie_lane_efuse *efuse; member
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
106 * Initialize the phy by setting the efuse data.
136 struct mtk_pcie_lane_efuse *efuse = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_read_for_lane() local
142 ret = nvmem_cell_read_variable_le_u32(dev, efuse_id, &efuse->tx_pmos); in mtk_pcie_efuse_read_for_lane()
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| /linux-6.12.1/drivers/cpufreq/ |
| D | ti-cpufreq.c | 87 unsigned long efuse);
107 unsigned long efuse) in amx3_efuse_xlate() argument
109 if (!efuse) in amx3_efuse_xlate()
110 efuse = opp_data->soc_data->efuse_fallback; in amx3_efuse_xlate()
112 return ~efuse; in amx3_efuse_xlate()
116 unsigned long efuse) in dra7_efuse_xlate() argument
121 * The efuse on dra7 and am57 parts contains a specific in dra7_efuse_xlate()
125 switch (efuse) { in dra7_efuse_xlate()
142 unsigned long efuse) in omap3_efuse_xlate() argument
145 return BIT(efuse); in omap3_efuse_xlate()
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| /linux-6.12.1/drivers/net/wireless/realtek/rtw88/ |
| D | efuse.c | 8 #include "efuse.h"
31 /* efuse header format
43 u32 physical_size = rtwdev->efuse.physical_size; in rtw_dump_logical_efuse_map()
44 u32 protect_size = rtwdev->efuse.protect_size; in rtw_dump_logical_efuse_map()
45 u32 logical_size = rtwdev->efuse.logical_size; in rtw_dump_logical_efuse_map()
90 u32 size = rtwdev->efuse.physical_size; in rtw_dump_physical_efuse_map()
149 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw_parse_efuse_map() local
150 u32 phy_size = efuse->physical_size; in rtw_parse_efuse_map()
151 u32 log_size = efuse->logical_size; in rtw_parse_efuse_map()
165 rtw_err(rtwdev, "failed to dump efuse physical map\n"); in rtw_parse_efuse_map()
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| D | main.c | 16 #include "efuse.h"
982 WARN(1, "invalid hw configuration from efuse\n"); in rtw_hw_config_rf_ant_num()
1196 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw_update_sta_info() local
1226 if (efuse->hw_cap.nss == 1 || rtwdev->hal.txrx_1ss) in rtw_update_sta_info()
1404 wifi_only = !rtwdev->efuse.btcoex; in rtw_power_on()
1545 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw_init_ht_cap() local
1558 if (efuse->hw_cap.bw & BIT(RTW_CHANNEL_WIDTH_40)) in rtw_init_ht_cap()
1565 if (efuse->hw_cap.nss > 1) { in rtw_init_ht_cap()
1581 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw_init_vht_cap() local
1585 if (efuse->hw_cap.ptcl != EFUSE_HW_CAP_IGNORE && in rtw_init_vht_cap()
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| /linux-6.12.1/drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | eeprom.c | 67 mt7603_has_cal_free_data(struct mt7603_dev *dev, u8 *efuse) in mt7603_has_cal_free_data() argument
69 if (!efuse[MT_EE_TEMP_SENSOR_CAL]) in mt7603_has_cal_free_data()
72 if (get_unaligned_le16(efuse + MT_EE_TX_POWER_0_START_2G) == 0) in mt7603_has_cal_free_data()
75 if (get_unaligned_le16(efuse + MT_EE_TX_POWER_1_START_2G) == 0) in mt7603_has_cal_free_data()
78 if (!efuse[MT_EE_CP_FT_VERSION]) in mt7603_has_cal_free_data()
81 if (!efuse[MT_EE_XTAL_FREQ_OFFSET]) in mt7603_has_cal_free_data()
84 if (!efuse[MT_EE_XTAL_WF_RFCAL]) in mt7603_has_cal_free_data()
91 mt7603_apply_cal_free_data(struct mt7603_dev *dev, u8 *efuse) in mt7603_apply_cal_free_data() argument
112 if (!mt7603_has_cal_free_data(dev, efuse)) in mt7603_apply_cal_free_data()
121 eeprom[offset] = efuse[offset]; in mt7603_apply_cal_free_data()
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| /linux-6.12.1/Documentation/devicetree/bindings/opp/ |
| D | ti,omap-opp-supply.yaml | 10 OMAP5, DRA7, and AM57 families of SoCs have Class 0 AVS eFuse
37 - description: OMAP5+ optimized voltages in efuse(Class 0) VDD along with
40 - description: OMAP5+ optimized voltages in efuse(class0) VDD but no VBB
52 ti,efuse-settings:
54 optimized efuse configuration.
63 - description: efuse offset where the optimized voltage is located
81 - ti,efuse-settings
95 ti,efuse-settings =
|