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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dgoogle,cros-ec-codec.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/sound/google,cros-ec-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Audio codec controlled by ChromeOS EC
10 - Cheng-Yi Chiang <cychiang@chromium.org>
11 - Tzung-Bi Shih <tzungbi@kernel.org>
14 Google's ChromeOS EC codec is a digital mic codec provided by the
15 Embedded Controller (EC) and is controlled via a host-command
16 interface. An EC codec node should only be found inside the "codecs"
[all …]
Dmt8183-mt6358-ts3a227-max98357.txt4 - compatible : "mediatek,mt8183_mt6358_ts3a227_max98357" for MAX98357A codec
5 "mediatek,mt8183_mt6358_ts3a227_max98357b" for MAX98357B codec
6 "mediatek,mt8183_mt6358_ts3a227_rt1015" for RT1015 codec
7 "mediatek,mt8183_mt6358_ts3a227_rt1015p" for RT1015P codec
8 - mediatek,platform: the phandle of MT8183 ASoC platform
11 - mediatek,headset-codec: the phandles of ts3a227 codecs
12 - mediatek,ec-codec: the phandle of EC codecs.
13 See google,cros-ec-codec.txt for more details.
14 - mediatek,hdmi-codec: the phandles of HDMI codec
20 mediatek,headset-codec = <&ts3a227>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mfd/
Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Guenter Roeck <groeck@chromium.org>
14 Google's ChromeOS EC is a microcontroller which talks to the AP and
16 The EC can be connected through various interfaces (I2C, SPI, and others)
22 - description:
23 For implementations of the EC connected through I2C.
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
32 power-supply = <&ppvar_sys>;
[all …]
Dmt8186-corsola.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
7 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
26 stdout-path = "serial0:115200n8";
35 backlight_lcd0: backlight-lcd0 {
36 compatible = "pwm-backlight";
[all …]
Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
[all …]
Dmt8173-elm.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/regulator/dlg,da9211-regulator.h>
9 #include <dt-bindings/gpio/gpio.h>
25 compatible = "pwm-backlight";
27 power-supply = <&bl_fixed_reg>;
28 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
30 pinctrl-names = "default";
31 pinctrl-0 = <&panel_backlight_en_pins>;
[all …]
/linux-6.12.1/sound/soc/codecs/
Dcros_ec_codec.c1 // SPDX-License-Identifier: GPL-2.0
5 * ChromeOS Embedded Controller codec driver.
7 * This driver uses the cros-ec interface to communicate with the ChromeOS
8 * EC for audio function.
71 return priv->ec_capabilities & BIT(cap); in ec_codec_capable()
83 return -ENOMEM; in send_ec_host_command()
85 msg->version = 0; in send_ec_host_command()
86 msg->command = cmd; in send_ec_host_command()
87 msg->outsize = outsize; in send_ec_host_command()
88 msg->insize = insize; in send_ec_host_command()
[all …]
D88pm860x-codec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * 88pm860x-codec.c -- 88PM860x ALSA SoC Audio Driver
26 #include "88pm860x-codec.h"
117 * This widget should be just after DAC & PGA in DAPM power-on sequence and
118 * before DAC & PGA in DAPM power-off sequence.
149 /* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */
150 static const DECLARE_TLV_DB_SCALE(dpga_tlv, -9450, 150, 1);
152 /* -9dB to 0db in 3dB steps */
153 static const DECLARE_TLV_DB_SCALE(adc_tlv, -900, 300, 0);
155 /* {-23, -17, -13.5, -11, -9, -6, -3, 0}dB */
[all …]
/linux-6.12.1/sound/pci/ali5451/
Dali5451.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * --
11 * --
21 #include <linux/dma-mapping.h>
141 #define ALI_REG(codec, x) ((codec)->port + x) argument
180 struct snd_ali *codec; member
185 int count; /* runtime->period_size */
187 /* --- */
264 static inline unsigned int snd_ali_5451_peek(struct snd_ali *codec, in snd_ali_5451_peek() argument
267 return (unsigned int)inl(ALI_REG(codec, port)); in snd_ali_5451_peek()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsc7280-herobrine.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
20 #include "sc7280-qcard.dtsi"
21 #include "sc7280-chrome-common.dtsi"
25 stdout-path = "serial0:115200n8";
38 ppvar_sys: ppvar-sys-regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "ppvar_sys";
[all …]
Dsc7180-trogdor.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/sc7180-lpass.h>
16 #include "sc7180-firmware-tfa.dtsi"
22 thermal-zones {
23 charger_thermal: charger-thermal {
[all …]
Dsc7180-acer-aspire1.dts1 // SPDX-License-Identifier: BSD-3-Clause
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/sound/qcom,q6asm.h>
7 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
14 /delete-node/ &tz_mem;
15 /delete-node/ &ipa_fw_mem;
20 chassis-type = "laptop";
30 stdout-path = "serial0:115200n8";
33 reserved-memory {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
15 /* EC turns on w/ pp900_ap_en; always on for AP */
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
[all …]
Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
9 #include "rk3399-op1.dtsi"
18 stdout-path = "serial2:115200n8";
27 * - Rails that only connect to the EC (or devices that the EC talks to)
29 * - Rails _are_ included if the rails go to the AP even if the AP
38 * - The EC controls the enable and the EC always enables a rail as
40 * - The rails are actually connected to each other by a jumper and
45 ppvar_sys: ppvar-sys {
[all …]
Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
11 chassis-type = "tablet";
16 pp1250_s3: pp1250-s3 {
17 compatible = "regulator-fixed";
18 regulator-name = "pp1250_s3";
20 /* EC turns on w/ pp1250_s3_en; always on for AP */
21 regulator-always-on;
22 regulator-boot-on;
[all …]
/linux-6.12.1/sound/soc/amd/
Dacp3x-rt5682-max9836.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Machine driver for AMD ACP Audio engine using DA7219 & MAX98357 codec.
11 #include <sound/soc-dapm.h>
50 EC, enumerator
56 struct snd_soc_card *card = rtd->card; in acp3x_5682_init()
58 struct snd_soc_component *component = codec_dai->component; in acp3x_5682_init()
60 dev_info(rtd->dev, "codec dai name = %s\n", codec_dai->name); in acp3x_5682_init()
67 dev_err(rtd->card->dev, in acp3x_5682_init()
72 /* set codec PLL */ in acp3x_5682_init()
76 dev_err(rtd->dev, "can't set rt5682 PLL: %d\n", ret); in acp3x_5682_init()
[all …]
/linux-6.12.1/drivers/platform/x86/dell/
Ddell-wmi-privacy.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/input/sparse-keymap.h>
19 #include "dell-wmi-privacy.h"
21 #define DELL_PRIVACY_GUID "6932965F-1671-4CEB-B988-D3AB0A901919"
78 return priv && (priv->features_present & BIT(DELL_PRIVACY_TYPE_AUDIO)); in dell_privacy_has_mic_mute()
86 * 3) WMI event is received by dell-privacy
87 * 4) KEY_MICMUTE emitted from dell-privacy
89 * 6) Codec kernel driver catches and calls ledtrig_audio_set which will call
91 * 7) dell-privacy notifies EC, the timeout is cancelled and the HW mute activates.
92 * If the EC is not notified then the HW mic mute will activate when the timeout
[all …]
/linux-6.12.1/drivers/media/platform/verisilicon/
Dhantro_v4l2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Hantro VPU codec driver
7 * Alpha Lin <Alpha.Lin@rock-chips.com>
8 * Jeffy Chen <jeffy.chen@rock-chips.com>
13 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
14 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-event.h>
25 #include <media/v4l2-mem2mem.h>
49 if (ctx->is_encoder) { in hantro_get_formats()
[all …]
/linux-6.12.1/arch/arm/boot/dts/amlogic/
Dmeson8b-ec100.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
35 gpio-keys {
36 compatible = "gpio-keys-polled";
[all …]
/linux-6.12.1/drivers/gpu/drm/bridge/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_DRM_AUX_BRIDGE) += aux-bridge.o
3 obj-$(CONFIG_DRM_AUX_HPD_BRIDGE) += aux-hpd-bridge.o
4 obj-$(CONFIG_DRM_CHIPONE_ICN6211) += chipone-icn6211.o
5 obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
6 obj-$(CONFIG_DRM_CROS_EC_ANX7688) += cros-ec-anx7688.o
7 obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
8 obj-$(CONFIG_DRM_FSL_LDB) += fsl-ldb.o
9 obj-$(CONFIG_DRM_ITE_IT6505) += ite-it6505.o
10 obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o
[all …]
/linux-6.12.1/arch/arm/boot/dts/samsung/
Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos5420-cpus.dtsi"
21 compatible = "google,pit-rev16",
[all …]
Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos5420-cpus.dtsi"
21 compatible = "google,pi-rev16",
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/thermal/thermal.h>
14 stdout-path = "serial0:115200n8";
20 * missing a unit-address. However, the bootloader on these Chromebook
22 * Adding the unit-address causes the bootloader to create a /memory
34 /delete-node/ memory@80000000;
40 vdd-supply = <&vdd_3v3_hdmi>;
41 pll-supply = <&vdd_hdmi_pll>;
42 hdmi-supply = <&vdd_5v0_hdmi>;
[all …]
/linux-6.12.1/include/linux/platform_data/
Dcros_ec_commands.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Host communication command constants for ChromeOS EC
7 * NOTE: This file is auto-generated from ChromeOS EC Open Source code from
8 * https://chromium.googlesource.com/chromiumos/platform/ec/+/master/include/ec_commands.h
11 /* Host communication command constants for Chrome EC */
52 * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
56 * MEC series EC; an attempt to address a larger region may fail.
63 /* EC command register bit functions */
65 #define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */
66 #define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */
[all …]

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