Home
last modified time | relevance | path

Searched +full:dt +full:- +full:mmio (Results 1 – 25 of 246) sorted by relevance

12345678910

/linux-6.12.1/tools/testing/selftests/devices/probe/boards/
Dgoogle,spherion.yaml1 # SPDX-License-Identifier: GPL-2.0
7 # The top-level is a list of controllers, either for USB or PCI(e).
8 # Every controller needs to have a 'type' key set to either 'usb-controller' or
9 # 'pci-controller'.
12 # - dt-mmio: identify the MMIO address of the controller as defined in the
14 # - of-fullname-regex: regular expression to match against the OF_FULLNAME
16 # sibling controllers. In this case, dt-mmio can't be used, and this property
18 # - usb-version: for USB controllers to differentiate between USB3 and USB2
20 # - acpi-uid: _UID property of the controller as supplied by the ACPI. Useful to
27 # The 'path' key is needed for every child device (that is, not top-level) to
[all …]
/linux-6.12.1/drivers/comedi/drivers/
Ddt3000.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
13 * Devices: [Data Translation] DT3001 (dt3000), DT3001-PGL, DT3002, DT3003,
14 * DT3003-PGL, DT3004, DT3005, DT3004-200
29 * since each board has an on-board DSP (Texas Instruments TMS320C52).
31 * bus-mastering DMA, which eliminates them from serious work.
49 * PCI BAR0 - dual-ported RAM location definitions (dev->mmio)
176 .name = "dt3001-pgl",
196 .name = "dt3003-pgl",
211 .name = "dt3005", /* a.k.a. 3004-200 */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/remoteproc/
Dfsl,imx-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Co-Processor
10 This binding provides support for ARM Cortex M4 Co-processor found on some NXP iMX SoCs.
13 - Peng Fan <peng.fan@nxp.com>
18 - fsl,imx6sx-cm4
19 - fsl,imx7d-cm4
20 - fsl,imx7ulp-cm4
[all …]
/linux-6.12.1/tools/testing/selftests/devices/probe/
Dtest_discoverable_devices.py2 # SPDX-License-Identifier: GPL-2.0
9 # The per-platform YAML file defining the devices to be tested is stored inside
10 # the boards/ directory and chosen based on DT compatible or DMI IDs (sys_vendor
38 pci_controller_sysfs_dir = "pci[0-9a-f]{4}:[0-9a-f]{2}"
57 re_dt_mmio = re.compile("OF_FULLNAME=.*@([0-9a-f]+)")
106 if controller["type"] == "pci-controller":
108 elif controller["type"] == "usb-controller":
117 if controller.get("dt-mmio"):
118 if str(controller["dt-mmio"]) != get_dt_mmio(c):
121 if controller.get("of-fullname-regex"):
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dbaikal,bt1-apb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 APB-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
15 which routes them to the AXI-APB bridge. This interface is a single master
22 - $ref: /schemas/simple-bus.yaml#
27 const: baikal,bt1-apb
[all …]
Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
23 accessible by means of the Baikal-T1 System Controller.
26 - $ref: /schemas/simple-bus.yaml#
[all …]
/linux-6.12.1/arch/arm64/boot/dts/apple/
Dt6001.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6001", "apple,arm-platform";
23 compatible = "simple-bus";
24 #address-cells = <2>;
[all …]
Dt6002.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6002", "apple,arm-platform";
22 #address-cells = <2>;
23 #size-cells = <2>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dqcom,pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
15 - enum:
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
19 - items:
[all …]
/linux-6.12.1/drivers/phy/hisilicon/
Dphy-histb-combphy.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
21 #include <dt-bindings/phy/phy.h>
45 void __iomem *mmio; member
56 void __iomem *reg = priv->mmio + COMBPHY_CFG_REG; in nano_register_write()
76 return (mode->fixed != PHY_NONE) ? true : false; in is_mode_fixed()
81 struct histb_combphy_mode *mode = &priv->mode; in histb_combphy_set_mode()
82 struct regmap *syscon = priv->syscon; in histb_combphy_set_mode()
88 switch (mode->select) { in histb_combphy_set_mode()
99 return -EINVAL; in histb_combphy_set_mode()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mux/
Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/hdmi/
Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
47 void __iomem *mmio; member
87 /* platform config data (ie. from DT, or pdata) */
118 writel(data, hdmi->mmio + reg); in hdmi_write()
123 return readl(hdmi->mmio + reg); in hdmi_read()
128 return readl(hdmi->qfprom_mmio + reg); in hdmi_qfprom_read()
162 void __iomem *mmio; member
171 writel(data, phy->mmio + reg); in hdmi_phy_write()
176 return readl(phy->mmio + reg); in hdmi_phy_read()
193 return -ENODEV; in msm_hdmi_pll_8960_init()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/qcom/
Dqcom,wcnss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
21 firmware-name:
27 qcom,mmio:
32 - qcom,riva"
33 - qcom,pronto"
35 qcom,smd-channels:
[all …]
/linux-6.12.1/drivers/iio/dac/
Dstm32-dac-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
21 #include "stm32-dac-core.h"
24 * struct stm32_dac_priv - stm32 DAC core private data
36 * struct stm32_dac_cfg - DAC configuration
61 ret = regulator_enable(priv->vref); in stm32_dac_core_hw_start()
67 ret = clk_prepare_enable(priv->pclk); in stm32_dac_core_hw_start()
76 regulator_disable(priv->vref); in stm32_dac_core_hw_start()
86 clk_disable_unprepare(priv->pclk); in stm32_dac_core_hw_stop()
87 regulator_disable(priv->vref); in stm32_dac_core_hw_stop()
[all …]
/linux-6.12.1/arch/arm/boot/dts/socionext/
Dmilbeaut-m10v.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
[all …]
/linux-6.12.1/drivers/ata/
Dlibahci_platform.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2004-2005 Red Hat, Inc.
37 * ahci_platform_enable_phys - Enable PHYs
40 * This function enables all the PHYs found in hpriv->phys, if any.
51 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
52 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
56 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
58 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
62 rc = phy_power_on(hpriv->phys[i]); in ahci_platform_enable_phys()
64 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
[all …]
Dahci_imx.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
21 #include <linux/hwmon-sysfs.h>
26 #define DRV_NAME "ahci-imx"
29 /* Timer 1-ms Register */
79 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
83 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) in imx_phy_crbit_assert() argument
90 crval = readl(mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
95 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
99 srval = readl(mmio + IMX_P0PHYSR); in imx_phy_crbit_assert()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iommu/
Darm,smmu-v3.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
15 revisions, replacing the MMIO register interface with in-memory command
21 pattern: "^iommu@[0-9a-f]*"
23 const: arm,smmu-v3
32 interrupt-names:
[all …]
/linux-6.12.1/sound/soc/sof/mediatek/mt8186/
Dmt8186.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
5 // Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
24 #include "../../sof-of-dev.h"
25 #include "../../sof-audio.h"
27 #include "../mtk-adsp-common.h"
29 #include "mt8186-clk.h"
44 struct adsp_priv *priv = sdev->pdata->hw_pdata; in mt8186_send_msg()
46 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data, in mt8186_send_msg()
47 msg->msg_size); in mt8186_send_msg()
49 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ); in mt8186_send_msg()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/misc/
Dqemu,vcpu-stall-detector.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/qemu,vcpu-stall-detector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 which is accessed through MMIO.
14 - Sebastian Ene <sebastianene@google.com>
19 - qemu,vcpu-stall-detector
24 clock-frequency:
35 timeout-sec:
43 - compatible
[all …]
/linux-6.12.1/drivers/phy/rockchip/
Dphy-rockchip-naneng-combphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
137 void __iomem *mmio; member
156 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
158 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
166 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
167 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
168 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
170 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
175 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dnxp,imx95-display-master-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
15 - const: nxp,imx95-display-master-csr
16 - const: syscon
21 power-domains:
27 '#clock-cells':
32 include/dt-bindings/clock/nxp,imx95-clock.h
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
32 - .../clock/clock-bindings.txt
33 - <dt-bindings/clock/tegra186-clock.h>
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/
Dwriting-bindings.rst1 .. SPDX-License-Identifier: GPL-2.0
11 Documentation/devicetree/bindings/submitting-patches.rst
17 - DO attempt to make bindings complete even if a driver doesn't support some
21 - DON'T refer to Linux or "device driver" in bindings. Bindings should be
24 - DO use node names matching the class of the device. Many standard names are
25 defined in the DT Spec. If there isn't one, consider adding it.
27 - DO check that the example matches the documentation especially after making
30 - DON'T create nodes just for the sake of instantiating drivers. Multi-function
31 devices only need child nodes when the child nodes have their own DT
34 - DON'T use 'syscon' alone without a specific compatible string. A 'syscon'
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/hwmon/
Dbaikal,bt1-pvt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 PVT Sensor
11 - Serge Semin <fancer.lancer@gmail.com>
14 Baikal-T1 SoC provides an embedded process, voltage and temperature
17 which may cause the system instability and even damages. The IP-block
19 control wrapper, which provides a MMIO registers-based access to the
20 sensor core functionality (APB3-bus based) and exposes an additional
[all …]

12345678910