Searched full:dpll1 (Results 1 – 10 of 10) sorted by relevance
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | sophgo,sg2042-clkgen.yaml | 31 - const: dpll1
59 "dpll1";
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 99 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
117 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
162 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
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| /linux-6.12.1/arch/arm/mach-omap1/ |
| D | opp_data.c | 17 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
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| D | clock_data.c | 686 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", in omap1_show_rates()
742 * divisors. See also omap1_clk_late_init() that can reprogram dpll1 in omap1_clk_init()
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| D | clock.c | 259 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */ in omap1_select_table_rate()
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| /linux-6.12.1/drivers/clk/sprd/ |
| D | sc9863a-clk.c | 34 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
271 static SPRD_PLL_HW(dpll1, "dpll1", &dpll1_gate.common.hw, 0x18, 3, itable_dpll,
276 static CLK_FIXED_FACTOR_HW(dpll1_400m, "dpll1-400m", &dpll0.common.hw, 4, 1, 0);
277 static CLK_FIXED_FACTOR_HW(dpll1_266m7, "dpll1-266m7", &dpll0.common.hw, 6, 1, 0);
278 static CLK_FIXED_FACTOR_HW(dpll1_123m1, "dpll1-123m1", &dpll0.common.hw, 13, 1, 0);
279 static CLK_FIXED_FACTOR_HW(dpll1_50m, "dpll1-50m", &dpll0.common.hw, 32, 1, 0);
284 &dpll1.common,
290 [CLK_DPLL1] = &dpll1.common.hw,
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| D | sc9860-clk.c | 54 static SPRD_SC_GATE_CLK(dpll1_gate, "dpll1-gate", "ext-26m", 0xb4,
175 static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, "dpll1", "dpll1-gate", 0x3c,
297 static CLK_FIXED_FACTOR(dpll1_50m, "dpll1-50m", "dpll1", 16, 1, 0);
506 "dpll0-50m", "dpll1-50m",
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| D | ums512-clk.c | 47 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x9c,
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| /linux-6.12.1/arch/riscv/boot/dts/sophgo/ |
| D | sg2042.dtsi | 194 "dpll1";
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| /linux-6.12.1/drivers/clk/sophgo/ |
| D | clk-sg2042-clkgen.c | 444 SG2042_GATE_FW(GATE_CLK_DDR23_DIV0, "clk_gate_ddr23_div0", "dpll1",
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