Home
last modified time | relevance | path

Searched full:dpll0 (Results 1 – 11 of 11) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dsophgo,sg2042-clkgen.yaml30 - const: dpll0
58 "dpll0",
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h95 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
113 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
158 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
Dintel_cdclk.c1044 * We always enable DPLL0 with the lowest link rate possible, but still in skl_dpll0_link_rate()
1072 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1086 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
3042 * DPLL0 VCO may need to be adjusted to get the correct in skl_dpll0_vco()
Dintel_dpll_mgr.c1477 /* DPLL0 is always enabled since it drives CDCLK */ in skl_ddi_dpll0_get_hw_state()
3943 * since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled. in adlp_cmtg_clock_gating_wa()
/linux-6.12.1/drivers/clk/sprd/
Dsc9863a-clk.c28 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
269 static SPRD_PLL_HW(dpll0, "dpll0", &dpll0_gate.common.hw, 0x0, 3, itable_dpll,
274 static CLK_FIXED_FACTOR_HW(dpll0_933m, "dpll0-933m", &dpll0.common.hw, 2, 1, 0);
275 static CLK_FIXED_FACTOR_HW(dpll0_622m3, "dpll0-622m3", &dpll0.common.hw, 3, 1, 0);
276 static CLK_FIXED_FACTOR_HW(dpll1_400m, "dpll1-400m", &dpll0.common.hw, 4, 1, 0);
277 static CLK_FIXED_FACTOR_HW(dpll1_266m7, "dpll1-266m7", &dpll0.common.hw, 6, 1, 0);
278 static CLK_FIXED_FACTOR_HW(dpll1_123m1, "dpll1-123m1", &dpll0.common.hw, 13, 1, 0);
279 static CLK_FIXED_FACTOR_HW(dpll1_50m, "dpll1-50m", &dpll0.common.hw, 32, 1, 0);
283 &dpll0.common,
289 [CLK_DPLL0] = &dpll0.common.hw,
[all …]
Dums512-clk.c45 static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
132 static SPRD_PLL_HW(dpll0, "dpll0", &dpll0_gate.common.hw, 0x4, 3,
134 static CLK_FIXED_FACTOR_HW(dpll0_58m31, "dpll0-58m31", &dpll0.common.hw,
139 &dpll0.common,
144 [CLK_DPLL0] = &dpll0.common.hw,
Dsc9860-clk.c52 static SPRD_SC_GATE_CLK(dpll0_gate, "dpll0-gate", "ext-26m", 0xb4,
172 static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, "dpll0", "dpll0-gate", 0x34,
296 static CLK_FIXED_FACTOR(dpll0_50m, "dpll0-50m", "dpll0", 16, 1, 0);
506 "dpll0-50m", "dpll1-50m",
/linux-6.12.1/drivers/gpu/drm/i915/gvt/
Ddisplay.c384 * setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x in emulate_monitor_status_change()
385 * so we fixed to DPLL0 here. in emulate_monitor_status_change()
386 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode in emulate_monitor_status_change()
/linux-6.12.1/arch/riscv/boot/dts/sophgo/
Dsg2042.dtsi193 "dpll0",
/linux-6.12.1/arch/arm64/boot/dts/sprd/
Dums512.dtsi250 dpll0: clock-controller@0 { label
/linux-6.12.1/drivers/clk/sophgo/
Dclk-sg2042-clkgen.c437 SG2042_GATE_FW(GATE_CLK_DDR01_DIV0, "clk_gate_ddr01_div0", "dpll0",