| /linux-6.12.1/drivers/phy/mediatek/ |
| D | phy-mtk-dp.c | 87 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_init() local
97 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE0_DRIVING_PARAM_3, in mtk_dp_phy_init()
99 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE1_DRIVING_PARAM_3, in mtk_dp_phy_init()
101 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE2_DRIVING_PARAM_3, in mtk_dp_phy_init()
103 regmap_bulk_write(dp_phy->regs, MTK_DP_LANE3_DRIVING_PARAM_3, in mtk_dp_phy_init()
111 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_configure() local
134 regmap_write(dp_phy->regs, MTK_DP_PHY_DIG_BIT_RATE, val); in mtk_dp_phy_configure()
137 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_PLL_CTL_1, in mtk_dp_phy_configure()
145 struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy); in mtk_dp_phy_reset() local
147 regmap_update_bits(dp_phy->regs, MTK_DP_PHY_DIG_SW_RST, in mtk_dp_phy_reset()
[all …]
|
| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 67 enum drm_dp_phy dp_phy) in intel_dp_lttpr_phy_caps() argument
69 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; in intel_dp_lttpr_phy_caps()
74 enum drm_dp_phy dp_phy) in intel_dp_read_lttpr_phy_caps() argument
76 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); in intel_dp_read_lttpr_phy_caps()
78 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { in intel_dp_read_lttpr_phy_caps()
79 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n"); in intel_dp_read_lttpr_phy_caps()
83 lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n", in intel_dp_read_lttpr_phy_caps()
307 enum drm_dp_phy dp_phy) in intel_dp_lttpr_voltage_max() argument
309 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); in intel_dp_lttpr_voltage_max()
318 enum drm_dp_phy dp_phy) in intel_dp_lttpr_preemph_max() argument
[all …]
|
| D | intel_dp_link_training.h | 27 enum drm_dp_phy dp_phy,
31 enum drm_dp_phy dp_phy,
35 enum drm_dp_phy dp_phy);
43 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
|
| /linux-6.12.1/include/drm/display/ |
| D | drm_dp.h | 1501 #define DP_LTTPR_BASE(dp_phy) \ argument
1503 ((dp_phy) - DP_PHY_LTTPR1))
1505 #define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ argument
1506 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1509 #define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ argument
1510 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1513 #define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ argument
1514 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1520 #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ argument
1521 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
[all …]
|
| D | drm_dp_helper.h | 48 enum drm_dp_phy dp_phy, bool uhbr);
50 enum drm_dp_phy dp_phy, bool uhbr);
72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
567 enum drm_dp_phy dp_phy,
624 enum drm_dp_phy dp_phy,
661 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy);
|
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | qcom,dispcc-sm6350.yaml | 62 <&dp_phy 0>,
63 <&dp_phy 1>;
|
| D | qcom,sc7180-dispcc.yaml | 62 <&dp_phy 0>,
63 <&dp_phy 1>;
|
| D | qcom,sc7280-dispcc.yaml | 66 <&dp_phy 0>,
67 <&dp_phy 1>,
|
| D | qcom,sm7150-dispcc.yaml | 68 <&dp_phy 0>,
69 <&dp_phy 1>;
|
| D | qcom,sdm845-dispcc.yaml | 74 <&dp_phy 0>,
75 <&dp_phy 1>;
|
| D | qcom,dispcc-sm6125.yaml | 87 <&dp_phy 0>,
88 <&dp_phy 1>,
|
| D | qcom,dispcc-sm8x50.yaml | 108 <&dp_phy 0>,
109 <&dp_phy 1>;
|
| /linux-6.12.1/Documentation/devicetree/bindings/display/msm/ |
| D | dp-controller.yaml | 206 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
208 phys = <&dp_phy>;
|
| D | qcom,sc7180-mdss.yaml | 272 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
273 phys = <&dp_phy>;
|
| D | qcom,sm7150-mdss.yaml | 404 assigned-clock-parents = <&dp_phy 0>,
405 <&dp_phy 1>;
410 phys = <&dp_phy>;
|
| D | qcom,sc7280-mdss.yaml | 392 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
393 phys = <&dp_phy>;
|
| /linux-6.12.1/drivers/gpu/drm/display/ |
| D | drm_dp_helper.c | 286 enum drm_dp_phy dp_phy, bool uhbr, bool cr) in __read_delay() argument
292 if (dp_phy == DP_PHY_DPRX) { in __read_delay()
313 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); in __read_delay()
320 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); in __read_delay()
341 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_clock_recovery_delay() argument
343 return __read_delay(aux, dpcd, dp_phy, uhbr, true); in drm_dp_read_clock_recovery_delay()
348 enum drm_dp_phy dp_phy, bool uhbr) in drm_dp_read_channel_eq_delay() argument
350 return __read_delay(aux, dpcd, dp_phy, uhbr, false); in drm_dp_read_channel_eq_delay()
409 * @dp_phy: The DP PHY identifier
411 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip,analogix-dp.yaml | 68 phys = <&dp_phy>;
|
| /linux-6.12.1/Documentation/devicetree/bindings/display/bridge/ |
| D | cdns,mhdp8546.yaml | 140 phys = <&dp_phy>;
|
| /linux-6.12.1/Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,exynos5-dp.yaml | 144 phys = <&dp_phy>;
|
| /linux-6.12.1/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-combo.c | 1642 struct phy *dp_phy; member
3495 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP in qmp_combo_parse_dt_lecacy_dp()
3657 return qmp->dp_phy; in qmp_combo_phy_xlate()
3744 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); in qmp_combo_probe()
3745 if (IS_ERR(qmp->dp_phy)) { in qmp_combo_probe()
3746 ret = PTR_ERR(qmp->dp_phy); in qmp_combo_probe()
3751 phy_set_drvdata(qmp->dp_phy, qmp); in qmp_combo_probe()
|
| /linux-6.12.1/arch/arm/boot/dts/samsung/ |
| D | exynos5250.dtsi | 298 dp_phy: dp-phy { label
1126 phys = <&dp_phy>;
|
| D | exynos5420.dtsi | 933 dp_phy: dp-phy { label
1213 phys = <&dp_phy>;
|