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/linux-6.12.1/net/dsa/
Dport.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2017 Savoir-faire Linux Inc.
22 * dsa_port_notify - Notify the switching fabric of changes to a port
23 * @dp: port on which change occurred
25 * @v: event-specific value.
29 * reconfigure themselves for cross-chip operations. Can also be used to
33 static int dsa_port_notify(const struct dsa_port *dp, unsigned long e, void *v) in dsa_port_notify() argument
35 return dsa_tree_notify(dp->ds->dst, e, v); in dsa_port_notify()
38 static void dsa_port_notify_bridge_fdb_flush(const struct dsa_port *dp, u16 vid) in dsa_port_notify_bridge_fdb_flush() argument
40 struct net_device *brport_dev = dsa_port_to_bridge_port(dp); in dsa_port_notify_bridge_fdb_flush()
[all …]
Dtag.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
29 return ops->needed_headroom + ops->needed_tailroom; in dsa_tag_protocol_overhead()
35 struct dsa_port *cpu_dp = dev->dsa_ptr; in dsa_conduit_find_user()
36 struct dsa_switch_tree *dst = cpu_dp->dst; in dsa_conduit_find_user()
37 struct dsa_port *dp; in dsa_conduit_find_user() local
39 list_for_each_entry(dp, &dst->ports, list) in dsa_conduit_find_user()
40 if (dp->ds->index == device && dp->index == port && in dsa_conduit_find_user()
41 dp->type == DSA_PORT_TYPE_USER) in dsa_conduit_find_user()
42 return dp->user; in dsa_conduit_find_user()
48 * dsa_software_untag_vlan_aware_bridge: Software untagging for VLAN-aware bridge
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Dtag_8021q.c1 // SPDX-License-Identifier: GPL-2.0
15 /* Binary structure of the fake 12-bit VID field (when the TPID is
19 * +-----------+-----+-----------------+-----------+-----------------------+
21 * +-----------+-----+-----------------+-----------+-----------------------+
23 * RSV - VID[11:10]:
26 * SWITCH_ID - VID[8:6]:
29 * VBID - { VID[9], VID[5:4] }:
30 * Virtual bridge ID. If between 1 and 7, packet targets the broadcast
31 * domain of a bridge. If transmitted as zero, packet targets a single
34 * PORT - VID[3:0]:
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Duser.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * net/dsa/user.c - user device handling
4 * Copyright (c) 2008-2009 Marvell Semiconductor
70 return ds->ops->port_fdb_add && ds->ops->port_fdb_del && in dsa_switch_supports_uc_filtering()
71 ds->fdb_isolation && !ds->vlan_filtering_is_global && in dsa_switch_supports_uc_filtering()
72 !ds->needs_standalone_vlan_filtering; in dsa_switch_supports_uc_filtering()
77 return ds->ops->port_mdb_add && ds->ops->port_mdb_del && in dsa_switch_supports_mc_filtering()
78 ds->fdb_isolation && !ds->vlan_filtering_is_global && in dsa_switch_supports_mc_filtering()
79 !ds->needs_standalone_vlan_filtering; in dsa_switch_supports_mc_filtering()
86 const unsigned char *addr = standalone_work->addr; in dsa_user_standalone_event_work()
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Dtrace.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Copyright 2022-2023 NXP
10 switch (db->type) { in dsa_db_print()
12 sprintf(buf, "port %s", db->dp->name); in dsa_db_print()
15 sprintf(buf, "lag %s id %d", db->lag.dev->name, db->lag.id); in dsa_db_print()
18 sprintf(buf, "bridge %s num %d", db->bridge.dev->name, in dsa_db_print()
19 db->bridge.num); in dsa_db_print()
27 const char *dsa_port_kind(const struct dsa_port *dp) in dsa_port_kind() argument
29 switch (dp->type) { in dsa_port_kind()
Ddsa.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2008-2009 Marvell Semiconductor
53 * dsa_lag_map() - Map LAG structure to a linear LAG array
59 * driver by setting ds->num_lag_ids. It is perfectly legal to leave
61 * no-ops.
67 for (id = 1; id <= dst->lags_len; id++) { in dsa_lag_map()
69 dst->lags[id - 1] = lag; in dsa_lag_map()
70 lag->id = id; in dsa_lag_map()
78 * driver can then return -EOPNOTSUPP back to DSA, which will in dsa_lag_map()
84 * dsa_lag_unmap() - Remove a LAG ID mapping
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Dtag_sja1105.c1 // SPDX-License-Identifier: GPL-2.0
23 /* Trap-to-host format (no trailer present) */
33 /* Meta frame format (for 2-step TX timestamps) */
74 return ds->tagger_data; in sja1105_tagger_private()
77 /* Similar to is_link_local_ether_addr(hdr->h_dest) but also covers PTP */
81 u64 dmac = ether_addr_to_u64(hdr->h_dest); in sja1105_is_link_local()
83 if (ntohs(hdr->h_proto) == ETH_P_SJA1105_META) in sja1105_is_link_local()
108 * Structure of the meta-data follow-up frame. in sja1105_meta_unpack()
114 * same and the E/T puts zeroes in the high-order byte, use in sja1105_meta_unpack()
117 packing(buf, &meta->tstamp, 31, 0, 4, UNPACK, 0); in sja1105_meta_unpack()
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/linux-6.12.1/drivers/gpu/drm/msm/dp/
Ddp_drm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
17 * dp_bridge_detect - callback to determine if connector is connected
18 * @bridge: Pointer to drm bridge structure
19 * Returns: Bridge's 'is connected' status
21 static enum drm_connector_status dp_bridge_detect(struct drm_bridge *bridge) in dp_bridge_detect() argument
23 struct msm_dp *dp; in dp_bridge_detect() local
25 dp = to_dp_bridge(bridge)->dp_display; in dp_bridge_detect()
27 drm_dbg_dp(dp->drm_dev, "link_ready = %s\n", in dp_bridge_detect()
28 (dp->link_ready) ? "true" : "false"); in dp_bridge_detect()
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Ddp_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
32 MODULE_PARM_DESC(psr_enabled, "enable PSR for eDP and DP displays");
165 { .compatible = "qcom,sc7180-dp", .data = &sc7180_dp_descs },
166 { .compatible = "qcom,sc7280-dp", .data = &sc7280_dp_descs },
167 { .compatible = "qcom,sc7280-edp", .data = &sc7280_dp_descs },
168 { .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_descs },
169 { .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_descs },
170 { .compatible = "qcom,sc8280xp-dp", .data = &sc8280xp_dp_descs },
171 { .compatible = "qcom,sc8280xp-edp", .data = &sc8280xp_dp_descs },
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/linux-6.12.1/drivers/gpu/drm/xlnx/
Dzynqmp_dp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
25 #include <linux/media-bus-format.h>
40 MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
47 MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
242 * struct zynqmp_dp_link_config - Common link config between source and sink
252 * struct zynqmp_dp_mode - Configured mode of DisplayPort
266 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
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Dzynqmp_dpsub.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
43 * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
54 * @bridge: The DP encoder bridge
57 * @dp: The DisplayPort controller
73 struct drm_bridge *bridge; member
77 struct zynqmp_dp *dp; member
/linux-6.12.1/drivers/gpu/drm/exynos/
Dexynos_dp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Samsung SoC DP (Display Port) interface driver.
21 #include <drm/bridge/analogix_dp.h>
51 struct exynos_dp_device *dp = to_dp(plat_data); in exynos_dp_crtc_clock_enable() local
52 struct drm_encoder *encoder = &dp->encoder; in exynos_dp_crtc_clock_enable()
54 if (!encoder->crtc) in exynos_dp_crtc_clock_enable()
55 return -EPERM; in exynos_dp_crtc_clock_enable()
57 exynos_drm_pipe_clk_enable(to_exynos_crtc(encoder->crtc), enable); in exynos_dp_crtc_clock_enable()
75 struct exynos_dp_device *dp = to_dp(plat_data); in exynos_dp_get_modes() local
78 if (dp->plat_data.panel) in exynos_dp_get_modes()
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/linux-6.12.1/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Analogix DP (Display Port) core interface driver.
21 #include <drm/bridge/analogix_dp.h>
39 static void analogix_dp_init_dp(struct analogix_dp_device *dp) in analogix_dp_init_dp() argument
41 analogix_dp_reset(dp); in analogix_dp_init_dp()
43 analogix_dp_swreset(dp); in analogix_dp_init_dp()
45 analogix_dp_init_analog_param(dp); in analogix_dp_init_dp()
46 analogix_dp_init_interrupt(dp); in analogix_dp_init_dp()
49 analogix_dp_enable_sw_function(dp); in analogix_dp_init_dp()
51 analogix_dp_config_interrupt(dp); in analogix_dp_init_dp()
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/linux-6.12.1/drivers/gpu/drm/bridge/
Dmegachips-stdpxxxx-ge-b850v3-fw.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for MegaChips STDP4028 with GE B850v3 firmware (LVDS-DP)
4 * Driver for MegaChips STDP2690 with GE B850v3 firmware (DP-DP++)
10 * This driver creates a drm_bridge and a drm_connector for the LVDS to DP++
11 * display bridge of the GE B850v3. There are two physical bridges on the video
12 * signal pipeline: a STDP4028(LVDS to DP) and a STDP2690(DP to DP++). The
19 * Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
61 struct drm_bridge bridge; member
71 struct i2c_adapter *adapter = client->adapter; in stdp2690_read_block()
76 .addr = client->addr, in stdp2690_read_block()
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Ddisplay-connector.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/media-bus-format.h>
21 struct drm_bridge bridge; member
31 to_display_connector(struct drm_bridge *bridge) in to_display_connector() argument
33 return container_of(bridge, struct display_connector, bridge); in to_display_connector()
36 static int display_connector_attach(struct drm_bridge *bridge, in display_connector_attach() argument
39 return flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR ? 0 : -EINVAL; in display_connector_attach()
43 display_connector_detect(struct drm_bridge *bridge) in display_connector_detect() argument
45 struct display_connector *conn = to_display_connector(bridge); in display_connector_detect()
47 if (conn->hpd_gpio) { in display_connector_detect()
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Dcros-ec-anx7688.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CrOS EC ANX7688 HDMI->DP bridge driver
38 struct drm_bridge bridge; member
43 bridge_to_cros_ec_anx7688(struct drm_bridge *bridge) in bridge_to_cros_ec_anx7688() argument
45 return container_of(bridge, struct cros_ec_anx7688, bridge); in bridge_to_cros_ec_anx7688()
48 static bool cros_ec_anx7688_bridge_mode_fixup(struct drm_bridge *bridge, in cros_ec_anx7688_bridge_mode_fixup() argument
52 struct cros_ec_anx7688 *anx = bridge_to_cros_ec_anx7688(bridge); in cros_ec_anx7688_bridge_mode_fixup()
58 if (!anx->filter) in cros_ec_anx7688_bridge_mode_fixup()
62 ret = regmap_bulk_read(anx->regmap, ANX7688_DP_BANDWIDTH_REG, regs, 2); in cros_ec_anx7688_bridge_mode_fixup()
81 requiredbw = mode->clock * 8 * 3; in cros_ec_anx7688_bridge_mode_fixup()
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/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence MHDP8546 bridge
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
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Dtoshiba,tc358767.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge
10 - Andrey Gusakov <andrey.gusakov@cogentembedded.com>
13 The TC358767/TC358867/TC9595 is bridge device which
14 converts DSI/DPI to eDP/DP .
19 - items:
20 - enum:
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Danalogix,dp.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/analogix,dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analogix Display Port bridge
10 - Rob Herring <robh@kernel.org>
21 clock-names: true
25 phy-names:
26 const: dp
28 force-hpd:
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/linux-6.12.1/drivers/gpu/drm/bridge/cadence/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Cadence DPI/DSI bridge"
11 Support Cadence DPI to DSI bridge. This is an internal
12 bridge and is meant to be directly embedded in a SoC.
25 tristate "Cadence DPI/DP bridge"
33 Support Cadence DPI to DP bridge. This is an internal
34 bridge and is meant to be directly embedded in a SoC.
36 in DP format.
42 bool "J721E Cadence DPI/DP wrapper support"
45 Support J721E Cadence DPI/DP wrapper. This is a wrapper
Dcdns-mhdp8546-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence MHDP8546 DP bridge driver.
7 * Authors: Quentin Schulz <quentin.schulz@free-electrons.com>
14 * - Implement optimized mailbox communication using mailbox interrupts
15 * - Add support for power management
16 * - Add support for features like audio, MST and fast link training
17 * - Implement request_fw_cancel to handle HW_STATE
18 * - Fix asynchronous loading of firmware implementation
19 * - Add DRM helper function for cdns_mhdp_lower_link_rate
29 #include <linux/media-bus-format.h>
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/linux-6.12.1/include/net/
Ddsa.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/net/dsa.h - Driver for Distributed Switch Architecture switch chips
4 * Copyright (c) 2008-2009 Marvell Semiconductor
125 /* Notifier chain for switch-wide events */
134 /* Maps offloaded LAG netdevs to a zero-based linear ID for
166 /* LAG IDs are one-based, the dst->lags array is zero-based */
168 for ((_id) = 1; (_id) <= (_dst)->lags_len; (_id)++) \
169 if ((_dst)->lags[(_id) - 1])
172 list_for_each_entry((_dp), &(_dst)->ports, list) \
176 list_for_each_entry((_dp), &(_ds)->dst->ports, list) \
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/linux-6.12.1/tools/testing/selftests/net/
Dtest_vxlan_mdb.sh2 # SPDX-License-Identifier: GPL-2.0
12 # +------------------------------------+ +------------------------------------+
19 # | +---------+---------+ | | +---------+---------+ |
33 # +-----------------|------------------+ +-----------------|------------------+
35 # +-----------------|------------------+ +-----------------|------------------+
49 # | +---------+---------+ | | +---------+---------+ |
56 # +------------------------------------+ +------------------------------------+
122 # All tests in this script. Can be overridden with -t option.
140 if [ ${rc} -eq ${expected} ]; then
141 printf "TEST: %-60s [ OK ]\n" "${msg}"
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/linux-6.12.1/tools/testing/selftests/drivers/net/mlxsw/
Ddevlink_trap_l3_drops.sh2 # SPDX-License-Identifier: GPL-2.0
4 # Test devlink-trap L3 drops functionality over mlxsw. Each registered L3 drop
8 # +---------------------------------+
16 # +----|----------------------------+
18 # +----|----------------------------------------------------------------------+
28 # +----|----------------------------------------------------------------------+
30 # +----|----------------------------+
38 # +---------------------------------+
67 ip -4 route add default vrf v$h1 nexthop via 192.0.2.2
68 ip -6 route add default vrf v$h1 nexthop via 2001:db8:1::2
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/linux-6.12.1/drivers/net/dsa/
Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
80 if (priv->bus) in mt7530_mutex_lock()
81 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
87 if (priv->bus) in mt7530_mutex_unlock()
88 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
94 struct mii_bus *bus = priv->bus; in core_write()
100 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
106 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
112 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
118 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
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