| /linux-6.12.1/arch/arm/kernel/ |
| D | dma.c | 3 * linux/arch/arm/kernel/dma.c
7 * Front-end to the DMA handling. This handles the allocation/freeing
8 * of DMA channels, and provides a unified interface to the machines
9 * DMA facilities.
19 #include <asm/dma.h>
21 #include <asm/mach/dma.h>
36 int __init isa_dma_add(unsigned int chan, dma_t *dma) in isa_dma_add() argument
38 if (!dma->d_ops) in isa_dma_add()
41 sg_init_table(&dma->buf, 1); in isa_dma_add()
45 dma_chan[chan] = dma; in isa_dma_add()
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| /linux-6.12.1/drivers/tty/serial/8250/ |
| D | 8250_dma.c | 3 * 8250_dma.c - DMA Engine API support for 8250.c
10 #include <linux/dma-mapping.h>
17 struct uart_8250_dma *dma = p->dma; in __dma_tx_complete() local
22 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, in __dma_tx_complete()
27 dma->tx_running = 0; in __dma_tx_complete()
29 uart_xmit_advance(&p->port, dma->tx_size); in __dma_tx_complete()
35 if (ret || !dma->tx_running) in __dma_tx_complete()
43 struct uart_8250_dma *dma = p->dma; in __dma_rx_complete() local
50 * New DMA Rx can be started during the completion handler before it in __dma_rx_complete()
54 dma_status = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); in __dma_rx_complete()
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| /linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
13 DMA channels and the address space of the DMA controller
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
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| /linux-6.12.1/drivers/i2c/busses/ |
| D | i2c-stm32.c | 11 /* Functions for DMA support */
17 struct stm32_i2c_dma *dma; in stm32_i2c_dma_request() local
21 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); in stm32_i2c_dma_request()
22 if (!dma) in stm32_i2c_dma_request()
25 /* Request and configure I2C TX dma channel */ in stm32_i2c_dma_request()
26 dma->chan_tx = dma_request_chan(dev, "tx"); in stm32_i2c_dma_request()
27 if (IS_ERR(dma->chan_tx)) { in stm32_i2c_dma_request()
28 ret = PTR_ERR(dma->chan_tx); in stm32_i2c_dma_request()
31 "can't request DMA tx channel\n"); in stm32_i2c_dma_request()
40 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); in stm32_i2c_dma_request()
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| /linux-6.12.1/drivers/media/platform/xilinx/ |
| D | xilinx-dma.c | 3 * Xilinx Video DMA
12 #include <linux/dma/xilinx_dma.h>
23 #include <media/videobuf2-dma-contig.h>
25 #include "xilinx-dma.h"
57 static int xvip_dma_verify_format(struct xvip_dma *dma) in xvip_dma_verify_format() argument
65 subdev = xvip_dma_remote_subdev(&dma->pad, &fmt.pad); in xvip_dma_verify_format()
73 if (dma->fmtinfo->code != fmt.format.code || in xvip_dma_verify_format()
74 dma->format.height != fmt.format.height || in xvip_dma_verify_format()
75 dma->format.width != fmt.format.width || in xvip_dma_verify_format()
76 dma->format.colorspace != fmt.format.colorspace) in xvip_dma_verify_format()
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| /linux-6.12.1/drivers/dma/ |
| D | Kconfig | 3 # DMA engine configuration
7 bool "DMA Engine support"
10 DMA engines can do asynchronous data transfers without
14 DMA Device drivers supported by the configured arch, it may
18 bool "DMA Engine debugging"
22 say N here. This enables DMA engine core and driver debugging.
25 bool "DMA Engine verbose debugging"
30 the DMA engine core and drivers.
35 comment "DMA Devices"
74 provide DMA engine support. This includes the original ARM
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| /linux-6.12.1/sound/core/ |
| D | isadma.c | 3 * ISA DMA support functions
9 * ISA DMA controllers.
15 #include <linux/isa-dma.h>
19 * snd_dma_program - program an ISA DMA transfer
20 * @dma: the dma number
22 * @size: the DMA transfer size
23 * @mode: the DMA transfer mode, DMA_MODE_XXX
25 * Programs an ISA DMA transfer for the given buffer.
27 void snd_dma_program(unsigned long dma, in snd_dma_program() argument
34 disable_dma(dma); in snd_dma_program()
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| /linux-6.12.1/Documentation/devicetree/bindings/dma/ |
| D | qcom,gpi.yaml | 4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
7 title: Qualcomm Technologies Inc GPI DMA controller
13 QCOM GPI DMA controller provides DMA capabilities for
17 - $ref: dma-controller.yaml#
23 - qcom,sdm845-gpi-dma
24 - qcom,sm6350-gpi-dma
27 - qcom,qcm2290-gpi-dma
28 - qcom,qdu1000-gpi-dma
29 - qcom,sc7280-gpi-dma
30 - qcom,sdx75-gpi-dma
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| D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
7 - #dma-cells: Should be set to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
16 - ti,dma-safe-map: Safe routing value for unused request lines
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
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| D | intel,ldma.yaml | 4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
7 title: Lightning Mountain centralized DMA controllers.
14 - $ref: dma-controller.yaml#
31 "#dma-cells":
34 The first cell is the peripheral's DMA request line.
38 dma-channels:
42 dma-channel-mask:
58 intel,dma-poll-cnt:
61 DMA descriptor polling counter is used to control the poling mechanism
64 intel,dma-byte-en:
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| D | sprd,sc9860-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/sprd,sc9860-dma.yaml#
7 title: Spreadtrum SC9860 DMA controller
10 There are three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP
11 DMA controller, it can or do not request the IRQ, which will save
12 system power without resuming system by DMA interrupts if AGCP DMA
22 const: sprd,sc9860-dma
33 - description: DMA enable clock
34 - description: optional ashb_eb clock, only for the AGCP DMA controller
42 '#dma-cells':
45 dma-channels:
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| D | fsl,mxs-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/fsl,mxs-dma.yaml#
7 title: Freescale Direct Memory Access (DMA) Controller from i.MX23/i.MX28
13 - $ref: dma-controller.yaml#
18 const: fsl,imx8qxp-dma-apbh
31 - fsl,imx6q-dma-apbh
32 - fsl,imx6sx-dma-apbh
33 - fsl,imx7d-dma-apbh
34 - fsl,imx8qxp-dma-apbh
35 - const: fsl,imx28-dma-apbh
37 - fsl,imx23-dma-apbh
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| D | owl-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
18 - $ref: dma-controller.yaml#
23 - actions,s500-dma
24 - actions,s700-dma
25 - actions,s900-dma
33 DMA channels.
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| D | allwinner,sun50i-a64-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/allwinner,sun50i-a64-dma.yaml#
7 title: Allwinner A64 DMA Controller
14 - $ref: dma-controller.yaml#
17 "#dma-cells":
24 - allwinner,sun20i-d1-dma
25 - allwinner,sun50i-a64-dma
26 - allwinner,sun50i-a100-dma
27 - allwinner,sun50i-h6-dma
29 - const: allwinner,sun8i-r40-dma
30 - const: allwinner,sun50i-a64-dma
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| /linux-6.12.1/drivers/comedi/drivers/ |
| D | comedi_isadma.c | 3 * COMEDI ISA DMA support functions
10 #include <linux/dma-mapping.h>
11 #include <linux/isa-dma.h>
16 * comedi_isadma_program - program and enable an ISA DMA transfer
17 * @desc: the ISA DMA cookie to program and enable
34 * comedi_isadma_disable - disable the ISA DMA channel
35 * @dma_chan: the DMA channel to disable
37 * Returns the residue (remaining bytes) left in the DMA transfer.
54 * comedi_isadma_disable_on_sample - disable the ISA DMA channel
55 * @dma_chan: the DMA channel to disable
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| /linux-6.12.1/Documentation/driver-api/ |
| D | dma-buf.rst | 1 Buffer Sharing and Synchronization (dma-buf)
4 The dma-buf subsystem provides the framework for sharing buffers for
5 hardware (DMA) access across multiple device drivers and subsystems, and
14 interact with the three main primitives offered by dma-buf:
16 - dma-buf, representing a sg_table and exposed to userspace as a file
19 - dma-fence, providing a mechanism to signal when an asynchronous
21 - dma-resv, which manages a set of dma-fences for a particular dma-buf
29 For more details on how to design your subsystem's API for dma-buf use, please
30 see Documentation/userspace-api/dma-buf-alloc-exchange.rst.
33 Shared DMA Buffers
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| /linux-6.12.1/drivers/misc/bcm-vk/ |
| D | bcm_vk_sg.c | 5 #include <linux/dma-mapping.h>
27 struct bcm_vk_dma *dma,
30 static int bcm_vk_dma_free(struct device *dev, struct bcm_vk_dma *dma);
36 struct bcm_vk_dma *dma, in bcm_vk_dma_alloc() argument
60 dma->nr_pages = last - first + 1; in bcm_vk_dma_alloc()
62 /* Allocate DMA pages */ in bcm_vk_dma_alloc()
63 dma->pages = kmalloc_array(dma->nr_pages, in bcm_vk_dma_alloc()
66 if (!dma->pages) in bcm_vk_dma_alloc()
69 dev_dbg(dev, "Alloc DMA Pages [0x%llx+0x%x => %d pages]\n", in bcm_vk_dma_alloc()
70 data, vkdata->size, dma->nr_pages); in bcm_vk_dma_alloc()
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| /linux-6.12.1/drivers/soc/ti/ |
| D | knav_dma.c | 12 #include <linux/dma-direction.h>
109 struct knav_dma_device *dma; member
212 /* wait for the dma to shut itself down */ in chan_teardown()
240 /* teardown the dma channel */ in chan_stop()
256 static void dma_hw_enable_all(struct knav_dma_device *dma) in dma_hw_enable_all() argument
260 for (i = 0; i < dma->max_tx_chan; i++) { in dma_hw_enable_all()
261 writel_relaxed(0, &dma->reg_tx_chan[i].mode); in dma_hw_enable_all()
262 writel_relaxed(DMA_ENABLE, &dma->reg_tx_chan[i].control); in dma_hw_enable_all()
267 static void knav_dma_hw_init(struct knav_dma_device *dma) in knav_dma_hw_init() argument
272 spin_lock(&dma->lock); in knav_dma_hw_init()
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| /linux-6.12.1/drivers/media/pci/ivtv/ |
| D | ivtv-udma.c | 3 User DMA
25 int ivtv_udma_fill_sg_list (struct ivtv_user_dma *dma, struct ivtv_dma_page_info *dma_page, int map… in ivtv_udma_fill_sg_list() argument
40 if (PageHighMem(dma->map[map_offset])) { in ivtv_udma_fill_sg_list()
43 if (dma->bouncemap[map_offset] == NULL) in ivtv_udma_fill_sg_list()
44 dma->bouncemap[map_offset] = alloc_page(GFP_KERNEL); in ivtv_udma_fill_sg_list()
45 if (dma->bouncemap[map_offset] == NULL) in ivtv_udma_fill_sg_list()
48 src = kmap_atomic(dma->map[map_offset]) + offset; in ivtv_udma_fill_sg_list()
49 memcpy(page_address(dma->bouncemap[map_offset]) + offset, src, len); in ivtv_udma_fill_sg_list()
52 sg_set_page(&dma->SGlist[map_offset], dma->bouncemap[map_offset], len, offset); in ivtv_udma_fill_sg_list()
55 sg_set_page(&dma->SGlist[map_offset], dma->map[map_offset], len, offset); in ivtv_udma_fill_sg_list()
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| /linux-6.12.1/drivers/media/pci/netup_unidvb/ |
| D | netup_unidvb_core.c | 58 /* DMA base address */
61 /* 8 DMA blocks * 128 packets * 188 bytes*/
64 /* DMA status bits */
70 * struct netup_dma_regs - the map of DMA module registers
73 * @start_addr_lo: DMA ring buffer start address, lower part
74 * @start_addr_hi: DMA ring buffer start address, higher part
75 * @size: DMA ring buffer size register
76 * * Bits [0-7]: DMA packet size, 188 bytes
79 * @timeout: DMA timeout in units of 8ns
112 static void netup_unidvb_queue_cleanup(struct netup_dma *dma);
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
3 This document explains the device tree bindings for the packet dma
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
8 CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
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| /linux-6.12.1/arch/arm/mach-rpc/ |
| D | dma.c | 3 * linux/arch/arm/mach-rpc/dma.c
7 * DMA functions specific to RiscPC architecture
12 #include <linux/dma-mapping.h>
16 #include <asm/dma.h>
22 #include <asm/mach/dma.h>
26 struct dma_struct dma; member
58 if (idma->dma.sg) { in iomd_get_next_sg()
76 if (idma->dma.sgcount > 1) { in iomd_get_next_sg()
77 idma->dma.sg = sg_next(idma->dma.sg); in iomd_get_next_sg()
78 idma->dma_addr = idma->dma.sg->dma_address; in iomd_get_next_sg()
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| /linux-6.12.1/drivers/thunderbolt/ |
| D | dma_port.c | 3 * Thunderbolt DMA configuration based mailbox support
48 * struct tb_dma_port - DMA control port
49 * @sw: Switch the DMA port belongs to
50 * @port: Switch port number where DMA capability is found
174 * The DMA (NHI) port is either 3, 5 or 7 depending on the in dma_find_port()
191 * dma_port_alloc() - Finds DMA control port from a switch pointed by route
192 * @sw: Switch from where find the DMA port
194 * Function checks if the switch NHI port supports DMA configuration
196 * DMA port structure. Returns %NULL if the capabity was not found.
198 * The DMA control port is functional also when the switch is in safe
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| /linux-6.12.1/drivers/gpu/drm/exynos/ |
| D | regs-fimc.h | 24 /* Y 1st frame start address for output DMA */
26 /* Y 2nd frame start address for output DMA */
28 /* Y 3rd frame start address for output DMA */
30 /* Y 4th frame start address for output DMA */
32 /* Cb 1st frame start address for output DMA */
34 /* Cb 2nd frame start address for output DMA */
36 /* Cb 3rd frame start address for output DMA */
38 /* Cb 4th frame start address for output DMA */
40 /* Cr 1st frame start address for output DMA */
42 /* Cr 2nd frame start address for output DMA */
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| /linux-6.12.1/Documentation/core-api/ |
| D | dma-isa-lpc.rst | 2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
9 uses the same DMA system so it will be around for quite some time.
14 To do ISA style DMA you need to include two headers::
16 #include <linux/dma-mapping.h>
17 #include <asm/dma.h>
19 The first is the generic DMA API used to convert virtual addresses to
20 bus addresses (see Documentation/core-api/dma-api.rst for details).
22 The second contains the routines specific to ISA DMA transfers. Since
30 The ISA DMA controller has some very strict requirements on which
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|