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/linux-6.12.1/Documentation/devicetree/bindings/media/i2c/
Ddongwoon,dw9768.yaml60 Indication of VCM internal clock dividing rate select, as one multiple
64 - 0 # Dividing Rate - 2
65 - 1 # Dividing Rate - 1
66 - 2 # Dividing Rate - 1/2
67 - 3 # Dividing Rate - 1/4
68 - 4 # Dividing Rate - 8
69 - 5 # Dividing Rate - 4
/linux-6.12.1/tools/perf/pmu-events/arch/x86/goldmontplus/
Dvirtual-memory.json34 …Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of …
70 …Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of …
79 … Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by numb…
124 …Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of …
/linux-6.12.1/drivers/media/i2c/
Ddw9768.c56 * Bit[2:0] Namely PRESC[2:0], set the internal clock dividing rate as follow.
71 * Tvib = (6.3ms + AACT[5:0] * 0.1ms) * Dividing Rate
72 * Dividing Rate is the internal clock dividing rate that is defined at
177 * Tvib = (6.3ms + AACT[5:0] * 0.1MS) * Dividing Rate.
/linux-6.12.1/Documentation/devicetree/bindings/clock/ti/
Ddivider.txt63 - ti,min-div : min divisor for dividing the input clock rate, only
65 - ti,max-div : max divisor for dividing the input clock rate, only needed
/linux-6.12.1/drivers/clk/starfive/
Dclk-starfive-jh7110-pll.c15 * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
16 * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
18 * Q1: frequency dividing ratio of post divider, set by 2^postdiv1[1:0], eg. 1, 2, 4 or 8.
/linux-6.12.1/drivers/gpu/drm/msm/
Dmsm_dsc_helper.h31 * such as dividing by different values depending on if widebus is enabled.
/linux-6.12.1/kernel/
DKconfig.hz40 on SMP and NUMA systems and exactly dividing by both PAL and
/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Dapple,i2c.yaml43 used. This frequency is generated by dividing the reference clock.
/linux-6.12.1/Documentation/hwmon/
Dltc4260.rst52 current by dividing the reported value by the sense resistor value in mOhm.
Dltc4261.rst52 current by dividing the reported value by the sense resistor value in mOhm.
Dltc2945.rst52 current by dividing the reported value by the sense resistor value in mOhm.
/linux-6.12.1/Documentation/devicetree/bindings/iio/adc/
Daspeed,ast2600-adc.yaml25 • Integrate dividing circuit for battery sensing.
/linux-6.12.1/arch/arm/include/asm/
Dkasan_def.h64 * As you would expect, >> 3 is equal to dividing by 8, meaning each
/linux-6.12.1/arch/sparc/vdso/
Dvclock_gettime.c319 * Assign before dividing to ensure that the division is in __vdso_gettimeofday()
355 * Assign before dividing to ensure that the division is in __vdso_gettimeofday_stick()
/linux-6.12.1/Documentation/devicetree/bindings/soc/fsl/
Dfsl,qman-portal.yaml53 determined by dividing any of the channel's 8 work queue
/linux-6.12.1/include/linux/
Disa.h99 * 1024 possible base addresses. Dividing the number of possible base addresses
Dnfs_iostat.h18 * difference between two instantaneous samples and dividing that
/linux-6.12.1/drivers/platform/x86/hp/hp-bioscfg/
Dsurestart-attributes.c13 * bytes. This value is calculated by dividing 4096 (page size) by
/linux-6.12.1/include/linux/sunrpc/
Dmetrics.h19 * and dividing that by the time between the samples.
/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/
Dbrcm,sf2.yaml53 - description: dividing of the switch core clock
/linux-6.12.1/scripts/coccinelle/misc/
Darray_size.cocci2 /// Use ARRAY_SIZE instead of dividing sizeof array with sizeof an element
/linux-6.12.1/Documentation/admin-guide/device-mapper/
Ddm-service-time.rst9 The service time for each path is estimated by dividing the total size
/linux-6.12.1/drivers/clk/rockchip/
Dclk-cpu.c192 * dividing the primary parent by the extra dividers that were in rockchip_cpuclk_pre_rate_change()
246 * NOTE: we do this in a single transaction so we're never dividing the in rockchip_cpuclk_post_rate_change()
/linux-6.12.1/drivers/clk/meson/
Dclk-dualdiv.c20 * The dividing can be switched to single or dual, with a counter
/linux-6.12.1/Documentation/core-api/
Dpin_user_pages.rst34 that's a natural dividing line, and a good point to make separate wrapper calls.
106 rather than dividing page->_refcount into bit fields, we simple add a medium-

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