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/linux-6.12.1/drivers/gpu/drm/i915/
DMakefile12 # Support compiling the display code separately for both i915 and xe
220 display/hsw_ips.o \
221 display/i9xx_plane.o \
222 display/i9xx_wm.o \
223 display/intel_alpm.o \
224 display/intel_atomic.o \
225 display/intel_atomic_plane.o \
226 display/intel_audio.o \
227 display/intel_bios.o \
228 display/intel_bw.o \
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/linux-6.12.1/drivers/gpu/drm/xe/
DMakefile146 # i915 Display compat #defines and #includes
148 -I$(src)/display/ext \
150 -I$(srctree)/drivers/gpu/drm/i915/display/ \
159 # Rule to build display code shared with i915
160 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
164 # Display code specific to xe
166 display/ext/i915_irq.o \
167 display/ext/i915_utils.o \
168 display/intel_fb_bo.o \
169 display/intel_fbdev_fb.o \
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/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_de.h13 static inline struct intel_uncore *__to_uncore(struct intel_display *display) in __to_uncore() argument
15 return &to_i915(display->drm)->uncore; in __to_uncore()
19 __intel_de_read(struct intel_display *display, i915_reg_t reg) in __intel_de_read() argument
23 intel_dmc_wl_get(display, reg); in __intel_de_read()
25 val = intel_uncore_read(__to_uncore(display), reg); in __intel_de_read()
27 intel_dmc_wl_put(display, reg); in __intel_de_read()
34 __intel_de_read8(struct intel_display *display, i915_reg_t reg) in __intel_de_read8() argument
38 intel_dmc_wl_get(display, reg); in __intel_de_read8()
40 val = intel_uncore_read8(__to_uncore(display), reg); in __intel_de_read8()
42 intel_dmc_wl_put(display, reg); in __intel_de_read8()
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Dintel_vrr.c20 struct intel_display *display = to_intel_display(connector); in intel_vrr_is_capable() local
46 return HAS_VRR(display) && in intel_vrr_is_capable()
92 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_vblank_exit_length() local
94 if (DISPLAY_VER(display) >= 13) in intel_vrr_vblank_exit_length()
115 struct intel_display *display = to_intel_display(crtc_state); in is_cmrr_frac_required() local
119 if (!HAS_CMRR(display)) in is_cmrr_frac_required()
163 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_compute_config() local
187 if (HAS_LRR(display)) in intel_vrr_compute_config()
247 if (DISPLAY_VER(display) >= 13) { in intel_vrr_compute_config()
259 struct intel_display *display = to_intel_display(crtc_state); in trans_vrr_ctl() local
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Dintel_pps.c21 static void vlv_steal_power_sequencer(struct intel_display *display,
29 struct intel_display *display = to_intel_display(intel_dp); in pps_name() local
30 struct drm_i915_private *i915 = to_i915(display->drm); in pps_name()
66 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_lock() local
67 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_lock()
74 mutex_lock(&display->pps.mutex); in intel_pps_lock()
82 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_unlock() local
83 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_unlock()
85 mutex_unlock(&display->pps.mutex); in intel_pps_unlock()
94 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_kick() local
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Dintel_fbc.c28 * compressing the amount of memory used by the display. It is total
33 * and having fewer memory pages opened and accessed for refreshing the display.
93 struct intel_display *display; member
157 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, in skl_fbc_min_cfb_stride() argument
171 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
185 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, in _intel_fbc_cfb_stride() argument
194 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
195 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); in _intel_fbc_cfb_stride()
202 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_stride() local
207 return _intel_fbc_cfb_stride(display, cpp, width, stride); in intel_fbc_cfb_stride()
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Dvlv_dsi_regs.h14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC… argument
169 #define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_T… argument
174 #define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_T… argument
179 #define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_T… argument
184 #define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DE… argument
189 #define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RE… argument
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Dintel_psr.c49 * Since Haswell Display controller supports Panel Self-Refresh on display
51 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
52 * when system is idle but display is on as it eliminates display refresh
54 * display is unchanged.
98 * When unmasked (nearly) all display register writes (eg. even
227 struct intel_display *display = to_intel_display(intel_dp); in psr_global_enabled() local
232 if (display->params.enable_psr == -1) in psr_global_enabled()
234 return display->params.enable_psr; in psr_global_enabled()
244 struct intel_display *display = to_intel_display(intel_dp); in psr2_global_enabled() local
251 if (display->params.enable_psr == 1) in psr2_global_enabled()
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Dvlv_dsi.c88 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty() local
94 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), in vlv_dsi_wait_for_fifo_empty()
96 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
99 static void write_data(struct intel_display *display, in write_data() argument
111 intel_de_write(display, reg, val); in write_data()
115 static void read_data(struct intel_display *display, in read_data() argument
122 u32 val = intel_de_read(display, reg); in read_data()
134 struct intel_display *display = to_intel_display(&intel_dsi->base); in intel_dsi_host_transfer() local
149 data_reg = MIPI_LP_GEN_DATA(display, port); in intel_dsi_host_transfer()
151 ctrl_reg = MIPI_LP_GEN_CTRL(display, port); in intel_dsi_host_transfer()
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Dintel_opregion.c84 u32 didl[8]; /* supported display devices ID list */
85 u32 cpdl[8]; /* currently presented display list */
86 u32 cadl[8]; /* currently active display list */
97 u32 did2[7]; /* extended supported display devices ID list */
98 u32 cpd2[7]; /* extended attached display devices list */
255 struct intel_display *display; member
271 static int check_swsci_function(struct intel_display *display, u32 function) in check_swsci_function() argument
273 struct intel_opregion *opregion = display->opregion; in check_swsci_function()
303 static int swsci(struct intel_display *display, in swsci() argument
307 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in swsci()
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Dintel_bios.c30 #include <drm/display/drm_dp_helper.h>
31 #include <drm/display/drm_dsc_helper.h>
50 * through other means. The configuration is mostly related to display
69 struct intel_display *display; member
148 bdb_find_section(struct intel_display *display, in bdb_find_section() argument
153 list_for_each_entry(entry, &display->vbt.bdb_blocks, node) { in bdb_find_section()
203 static size_t lfp_data_min_size(struct intel_display *display) in lfp_data_min_size() argument
208 ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS); in lfp_data_min_size()
363 static void *generate_lfp_data_ptrs(struct intel_display *display, in generate_lfp_data_ptrs() argument
377 if (display->vbt.version < 155) in generate_lfp_data_ptrs()
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Dintel_opregion.h37 int intel_opregion_setup(struct intel_display *display);
38 void intel_opregion_cleanup(struct intel_display *display);
40 void intel_opregion_register(struct intel_display *display);
41 void intel_opregion_unregister(struct intel_display *display);
43 void intel_opregion_resume(struct intel_display *display);
44 void intel_opregion_suspend(struct intel_display *display,
47 bool intel_opregion_asle_present(struct intel_display *display);
48 void intel_opregion_asle_intr(struct intel_display *display);
51 int intel_opregion_notify_adapter(struct intel_display *display,
53 int intel_opregion_get_panel_type(struct intel_display *display);
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Dintel_dmc_wl.c16 * Wake lock is the mechanism to cause display engine to exit DC
26 * The wakelock mechanism in DMC allows the display engine to exit DC
29 * implicitly when the display engine accessed a register. With the
54 static void __intel_dmc_wl_release(struct intel_display *display) in __intel_dmc_wl_release() argument
56 struct drm_i915_private *i915 = to_i915(display->drm); in __intel_dmc_wl_release()
57 struct intel_dmc_wl *wl = &display->wl; in __intel_dmc_wl_release()
69 struct intel_display *display = in intel_dmc_wl_work() local
79 __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0); in intel_dmc_wl_work()
81 if (__intel_de_wait_for_register_nowl(display, DMC_WAKELOCK1_CTL, in intel_dmc_wl_work()
110 static bool __intel_dmc_wl_supported(struct intel_display *display) in __intel_dmc_wl_supported() argument
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Dintel_display_driver.c5 * High level display driver entry points. This is a layer between top level
6 * driver code and low level display functionality; no low level display code or
12 #include <drm/display/drm_dp_mst_helper.h>
90 cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); in intel_display_driver_init_hw()
93 intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
94 cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; in intel_display_driver_init_hw()
119 INIT_LIST_HEAD(&i915->display.global.obj_list); in intel_mode_config_init()
186 spin_lock_init(&i915->display.fb_tracking.lock); in intel_display_driver_early_probe()
187 mutex_init(&i915->display.backlight.lock); in intel_display_driver_early_probe()
188 mutex_init(&i915->display.audio.mutex); in intel_display_driver_early_probe()
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Dintel_hdmi.c35 #include <drm/display/drm_hdcp_helper.h>
36 #include <drm/display/drm_hdmi_helper.h>
37 #include <drm/display/drm_scdc_helper.h>
66 struct intel_display *display = to_intel_display(intel_hdmi); in assert_hdmi_port_disabled() local
69 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; in assert_hdmi_port_disabled()
71 drm_WARN(display->drm, in assert_hdmi_port_disabled()
72 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
77 assert_hdmi_transcoder_func_disabled(struct intel_display *display, in assert_hdmi_transcoder_func_disabled() argument
80 drm_WARN(display->drm, in assert_hdmi_transcoder_func_disabled()
81 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
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Dintel_hti.c12 void intel_hti_init(struct intel_display *display) in intel_hti_init() argument
16 * any display resources before we create our display outputs. in intel_hti_init()
18 if (DISPLAY_INFO(display)->has_hti) in intel_hti_init()
19 display->hti.state = intel_de_read(display, HDPORT_STATE); in intel_hti_init()
22 bool intel_hti_uses_phy(struct intel_display *display, enum phy phy) in intel_hti_uses_phy() argument
24 if (drm_WARN_ON(display->drm, phy == PHY_NONE)) in intel_hti_uses_phy()
27 return display->hti.state & HDPORT_ENABLED && in intel_hti_uses_phy()
28 display->hti.state & HDPORT_DDI_USED(phy); in intel_hti_uses_phy()
31 u32 intel_hti_dpll_mask(struct intel_display *display) in intel_hti_dpll_mask() argument
33 if (!(display->hti.state & HDPORT_ENABLED)) in intel_hti_dpll_mask()
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Dintel_quirks.c12 static void intel_set_quirk(struct intel_display *display, enum intel_quirk_id quirk) in intel_set_quirk() argument
14 display->quirks.mask |= BIT(quirk); in intel_set_quirk()
25 static void quirk_ssc_force_disable(struct intel_display *display) in quirk_ssc_force_disable() argument
27 intel_set_quirk(display, QUIRK_LVDS_SSC_DISABLE); in quirk_ssc_force_disable()
28 drm_info(display->drm, "applying lvds SSC disable quirk\n"); in quirk_ssc_force_disable()
35 static void quirk_invert_brightness(struct intel_display *display) in quirk_invert_brightness() argument
37 intel_set_quirk(display, QUIRK_INVERT_BRIGHTNESS); in quirk_invert_brightness()
38 drm_info(display->drm, "applying inverted panel brightness quirk\n"); in quirk_invert_brightness()
42 static void quirk_backlight_present(struct intel_display *display) in quirk_backlight_present() argument
44 intel_set_quirk(display, QUIRK_BACKLIGHT_PRESENT); in quirk_backlight_present()
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Dintel_hotplug.c36 * Simply put, hotplug occurs when a display is connected to or disconnected
38 * Display Port short pulses and MST devices involved, complicating matters.
49 * further processing to appropriate bottom halves (Display Port specific and
52 * The Display Port work function i915_digport_work_func() calls into
72 * seen when display port sink is connected, hence on platforms whose DP
75 * this is specific to DP sinks handled by this routine and any other display
127 * stored in @dev_priv->display.hotplug.hpd_storm_threshold which defaults to
133 * &dev_priv->display.hotplug.hpd_storm_threshold. However, some older systems also
148 struct intel_hotplug *hpd = &dev_priv->display.hotplug; in intel_hpd_irq_storm_detect()
156 (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled)) in intel_hpd_irq_storm_detect()
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Dintel_sprite.c51 static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite) in sprite_name() argument
53 return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A'; in sprite_name()
70 struct intel_display *display = to_intel_display(plane->base.dev); in chv_sprite_update_csc() local
103 intel_de_write_fw(display, SPCSCYGOFF(plane_id), in chv_sprite_update_csc()
105 intel_de_write_fw(display, SPCSCCBOFF(plane_id), in chv_sprite_update_csc()
107 intel_de_write_fw(display, SPCSCCROFF(plane_id), in chv_sprite_update_csc()
110 intel_de_write_fw(display, SPCSCC01(plane_id), in chv_sprite_update_csc()
112 intel_de_write_fw(display, SPCSCC23(plane_id), in chv_sprite_update_csc()
114 intel_de_write_fw(display, SPCSCC45(plane_id), in chv_sprite_update_csc()
116 intel_de_write_fw(display, SPCSCC67(plane_id), in chv_sprite_update_csc()
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Dg4x_dp.c92 struct intel_display *display = to_intel_display(encoder); in intel_dp_prepare() local
122 intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED; in intel_dp_prepare()
144 intel_de_rmw(display, TRANS_DP_CTL(crtc->pipe), in intel_dp_prepare()
170 struct intel_display *display = to_intel_display(intel_dp); in assert_dp_port() local
173 bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN; in assert_dp_port()
184 struct intel_display *display = &dev_priv->display; in assert_edp_pll() local
185 bool cur_state = intel_de_read(display, DP_A) & DP_PLL_ENABLE; in assert_edp_pll()
197 struct intel_display *display = to_intel_display(intel_dp); in ilk_edp_pll_on() local
205 drm_dbg_kms(display->drm, "enabling eDP PLL for clock %d\n", in ilk_edp_pll_on()
215 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_on()
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Dintel_dp_aux.c21 static const char *aux_ch_name(struct intel_display *display, in aux_ch_name() argument
24 if (DISPLAY_VER(display) >= 13 && aux_ch >= AUX_CH_D_XELPD) in aux_ch_name()
26 else if (DISPLAY_VER(display) >= 12 && aux_ch >= AUX_CH_USBC1) in aux_ch_name()
59 struct intel_display *display = to_intel_display(intel_dp); in intel_dp_aux_wait_done() local
65 ret = intel_de_wait_custom(display, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY, in intel_dp_aux_wait_done()
70 drm_err(display->drm, in intel_dp_aux_wait_done()
79 struct intel_display *display = to_intel_display(intel_dp); in g4x_get_aux_clock_divider() local
88 return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(display)->rawclk_freq, 2000); in g4x_get_aux_clock_divider()
93 struct intel_display *display = to_intel_display(intel_dp); in ilk_get_aux_clock_divider() local
106 freq = display->cdclk.hw.cdclk; in ilk_get_aux_clock_divider()
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/linux-6.12.1/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-display-engine.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
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/linux-6.12.1/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst5 On this page, we try to keep track of acronyms related to the display
37 * DISPCLK: Display Clock
39 * DCFCLK: Display Controller Fabric Clock
56 Display Abstraction layer
59 Display Core
62 Display Controller
68 Display Controller Engine
71 Display Controller HUB
80 Display Core Next
83 Display Clock Generator block
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/linux-6.12.1/drivers/media/platform/renesas/vsp1/
Dvsp1_dl.c3 * vsp1_dl.c -- R-Car VSP1 Display List
41 * struct vsp1_dl_ext_header - Extended display list header
45 * @pre_ext_dl_plist: start address of pre-extended display list bodies
47 * @post_ext_dl_plist: start address of post-extended display list bodies
79 * struct vsp1_pre_ext_dl_body - Pre Extended Display List Body
80 * @opcode: Extended display list command operation code
93 * struct vsp1_dl_body - Display list body
94 * @list: entry in the display list list of bodies
121 * struct vsp1_dl_body_pool - display list body pool
145 * struct vsp1_dl_cmd_pool - Display List commands pool
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/linux-6.12.1/drivers/soc/sunxi/
Dsunxi_mbus.c13 * The display engine virtual devices are not strictly speaking
18 "allwinner,sun4i-a10-display-engine",
19 "allwinner,sun5i-a10s-display-engine",
20 "allwinner,sun5i-a13-display-engine",
21 "allwinner,sun6i-a31-display-engine",
22 "allwinner,sun6i-a31s-display-engine",
23 "allwinner,sun7i-a20-display-engine",
24 "allwinner,sun8i-a23-display-engine",
25 "allwinner,sun8i-a33-display-engine",
26 "allwinner,sun9i-a80-display-engine",
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