Searched full:diagrams (Results 1 – 25 of 32) sorted by relevance
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6 * Most of this code is based on the SDL diagrams published in the 7th ARRL7 * Computer Networking Conference papers. The diagrams have mistakes in them,9 * diagrams as the code is not obvious and probably very easy to break.
9 * Most of this code is based on the SDL diagrams published in the 7th ARRL10 * Computer Networking Conference papers. The diagrams have mistakes in them,12 * diagrams as the code is not obvious and probably very easy to break.
6 * Check out the links above for our tutorials and wiring diagrams
46 correctly draw the states diagrams and to calculate accurate statistics etc.
169 between diagrams::229 Abbreviations used in the diagrams::463 the links drawn between diagrams. For each of the map_elts, you can | | |466 arrows between the two diagrams show the linkages between those | | |687 Abbreviations used in the diagrams::
41 model. Trial and error is highly recommended; the pinout diagrams
44 and spatial order of fields. The diagrams below should make this
20 * The following tables represent the timing diagrams found in
51 Path diagrams
68 * This is T3-max on eDP timing diagrams or the delay from power on79 * This is (T3+T4+T5+T6+T8)-min on eDP timing diagrams or after the116 * This is not specified in a standard way on eDP timing diagrams.129 * This is (T6-min + max(T7-max, T8-min)) on eDP timing diagrams or142 * data) on eDP timing diagrams. It is not common to set.157 * This is T12-min on eDP timing diagrams.
43 These diagrams all look roughly like this, sometimes labeled with
46 This matches the timing diagrams often found in data sheets.
112 through dot to generate diagrams in many graphical formats::
153 So, as can be seen from the two diagrams (the parts marked as "Common code"),
283 * provided timing diagrams in the manual, positive polarity in sun4i_csi_start_streaming()
219 * The PL111 manual does not contain proper timining diagrams in pl111_display_enable()
202 API. The example sysfs paths and diagrams are relative to the Example
504 For those who like diagrams, I have created two "virtual subnets" on the
113 but their timing diagrams will make the CPOL and CPHA modes clear.
109 i.MX6Q SabreAuto. Refer to these diagrams in the entity descriptions
615 * These diagrams are synchronized on time and the voltage and current
195 necessary to abbreviate this pattern in the diagrams in the next
44 * These diagrams are only for the 10Gb link period
229 | See the following diagrams to see how this works. |
231 * STATE DIAGRAMS