Searched +full:desired +full:- +full:num +full:- +full:phases (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#13 controller that are not already included in the synopsys-dw-mshc-common.yaml17 - $ref: synopsys-dw-mshc-common.yaml#20 - Heiko Stuebner <heiko@sntech.de>27 - const: rockchip,rk2928-dw-mshc29 - const: rockchip,rk3288-dw-mshc30 - items:[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later11 #include <linux/mmc/slot-gpio.h>16 #include "dw_mmc-pltfm.h"41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to46 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_get_internal_phase()78 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()79 struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; in rockchip_mmc_get_phase()81 if (priv->internal_phase) in rockchip_mmc_get_phase()89 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_set_internal_phase()108 dev_err(host->dev, "%s: invalid clk rate\n", __func__); in rockchip_mmc_set_internal_phase()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */4 * Copyright 2009-2018 Solarflare Communications Inc.5 * Copyright 2019-2020 Xilinx Inc.13 /* Power-on reset state */35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */38 /* The rest of these are firmware-defined */46 /* Values to be written to the per-port status dword in shared71 * | | \--- Response72 * | \------- Error73 * \------------------------------ Resync (always set)[all …]