Searched full:define (Results 1 – 25 of 11426) sorted by relevance
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| D | nbio_7_2_0_offset.h | 22 #define _nbio_7_2_0_OFFSET_HEADER
27 #define cfgBIF_CFG_DEV0_RC_VENDOR_ID …
28 #define cfgBIF_CFG_DEV0_RC_DEVICE_ID …
29 #define cfgBIF_CFG_DEV0_RC_COMMAND …
30 #define cfgBIF_CFG_DEV0_RC_STATUS …
31 #define cfgBIF_CFG_DEV0_RC_REVISION_ID …
32 #define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE …
33 #define cfgBIF_CFG_DEV0_RC_SUB_CLASS …
34 #define cfgBIF_CFG_DEV0_RC_BASE_CLASS …
35 #define cfgBIF_CFG_DEV0_RC_CACHE_LINE …
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| D | nbio_7_7_0_offset.h | 24 #define _nbio_7_7_0_OFFSET_HEADER
30 #define cfgNBCFG_SCRATCH_4 …
35 #define cfgBIF_CFG_DEV0_RC_VENDOR_ID …
36 #define cfgBIF_CFG_DEV0_RC_DEVICE_ID …
37 #define cfgBIF_CFG_DEV0_RC_COMMAND …
38 #define cfgBIF_CFG_DEV0_RC_STATUS …
39 #define cfgBIF_CFG_DEV0_RC_REVISION_ID …
40 #define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE …
41 #define cfgBIF_CFG_DEV0_RC_SUB_CLASS …
42 #define cfgBIF_CFG_DEV0_RC_BASE_CLASS …
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| D | nbio_4_3_0_offset.h | 24 #define _nbio_4_3_0_OFFSET_HEADER
30 #define regBIF_BX0_PCIE_INDEX …
31 #define regBIF_BX0_PCIE_INDEX_BASE_IDX …
32 #define regBIF_BX0_PCIE_DATA …
33 #define regBIF_BX0_PCIE_DATA_BASE_IDX …
34 #define regBIF_BX0_PCIE_INDEX2 …
35 #define regBIF_BX0_PCIE_INDEX2_BASE_IDX …
36 #define regBIF_BX0_PCIE_DATA2 …
37 #define regBIF_BX0_PCIE_DATA2_BASE_IDX …
38 #define regBIF_BX0_PCIE_INDEX_HI …
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| D | nbio_7_11_0_offset.h | 24 #define _nbio_7_11_0_OFFSET_HEADER
30 #define cfgNBCFG_SCRATCH_0 …
31 #define cfgNBCFG_SCRATCH_1 …
32 #define cfgNBCFG_SCRATCH_2 …
33 #define cfgNBCFG_SCRATCH_3 …
34 #define cfgNBCFG_SCRATCH_4 …
43 #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV …
48 #define regNB_NBCFG0_NB_VENDOR_ID …
49 #define regNB_NBCFG0_NB_VENDOR_ID_BASE_IDX …
50 #define regNB_NBCFG0_NB_DEVICE_ID …
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dce/ |
| D | dce_12_0_offset.h | 22 #define _dce_12_0_OFFSET_HEADER
28 #define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR …
29 #define mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX …
34 #define mmdispdec_VGA_MEM_READ_PAGE_ADDR …
35 #define mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX …
40 #define mmDC_PERFMON0_PERFCOUNTER_CNTL …
41 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX …
42 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2 …
43 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX …
44 #define mmDC_PERFMON0_PERFCOUNTER_STATE …
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/dcn/ |
| D | dcn_4_1_0_offset.h | 6 #define _dcn_4_1_0_OFFSET_HEADER
12 #define regDENTIST_DISPCLK_CNTL …
13 #define regDENTIST_DISPCLK_CNTL_BASE_IDX …
18 #define regPHYPLLA_PIXCLK_RESYNC_CNTL …
19 #define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX …
20 #define regPHYPLLB_PIXCLK_RESYNC_CNTL …
21 #define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX …
22 #define regPHYPLLC_PIXCLK_RESYNC_CNTL …
23 #define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX …
24 #define regPHYPLLD_PIXCLK_RESYNC_CNTL …
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| D | dcn_3_0_2_offset.h | 22 #define _dcn_3_0_2_OFFSET_HEADER
28 #define mmVGA_MEM_WRITE_PAGE_ADDR …
29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX …
30 #define mmVGA_MEM_READ_PAGE_ADDR …
31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX …
32 #define mmVGA_RENDER_CONTROL …
33 #define mmVGA_RENDER_CONTROL_BASE_IDX …
34 #define mmVGA_SEQUENCER_RESET_CONTROL …
35 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX …
36 #define mmVGA_MODE_CONTROL …
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| D | dcn_3_0_0_offset.h | 3 #define _dcn_3_0_0_OFFSET_HEADER
9 #define mmVGA_MEM_WRITE_PAGE_ADDR …
10 #define mmVGA_MEM_WRITE_PAGE_ADDR …
11 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX …
12 #define mmVGA_MEM_READ_PAGE_ADDR …
13 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX …
14 #define mmVGA_RENDER_CONTROL …
15 #define mmVGA_RENDER_CONTROL_BASE_IDX …
16 #define mmVGA_SEQUENCER_RESET_CONTROL …
17 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX …
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| D | dcn_2_1_0_offset.h | 22 #define _dcn_2_1_0_OFFSET_HEADER
28 #define mmVGA_MEM_WRITE_PAGE_ADDR …
29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX …
30 #define mmVGA_MEM_READ_PAGE_ADDR …
31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX …
36 #define mmCRTC8_IDX …
37 #define mmCRTC8_IDX_BASE_IDX …
38 #define mmCRTC8_DATA …
39 #define mmCRTC8_DATA_BASE_IDX …
40 #define mmGENFC_WT …
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| D | dcn_3_2_0_offset.h | 22 #define _dcn_3_2_0_OFFSET_HEADER
28 #define regDENTIST_DISPCLK_CNTL …
29 #define regDENTIST_DISPCLK_CNTL_BASE_IDX …
34 #define regPHYPLLA_PIXCLK_RESYNC_CNTL …
35 #define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX …
36 #define regPHYPLLB_PIXCLK_RESYNC_CNTL …
37 #define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX …
38 #define regPHYPLLC_PIXCLK_RESYNC_CNTL …
39 #define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX …
40 #define regPHYPLLD_PIXCLK_RESYNC_CNTL …
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| D | dcn_3_1_6_offset.h | 25 #define _dcn_3_1_6_OFFSET_HEADER
31 #define regAZCONTROLLER0_GLOBAL_CAPABILITIES …
32 #define regAZCONTROLLER0_GLOBAL_CAPABILITIES_BASE_IDX …
33 #define regAZCONTROLLER0_MINOR_VERSION …
34 #define regAZCONTROLLER0_MINOR_VERSION_BASE_IDX …
35 #define regAZCONTROLLER0_MAJOR_VERSION …
36 #define regAZCONTROLLER0_MAJOR_VERSION_BASE_IDX …
37 #define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY …
38 #define regAZCONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX …
39 #define regAZCONTROLLER0_INPUT_PAYLOAD_CAPABILITY …
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| D | dcn_2_0_0_offset.h | 22 #define _dcn_2_0_0_OFFSET_HEADER
28 #define mmVGA_MEM_WRITE_PAGE_ADDR …
29 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX …
30 #define mmVGA_MEM_READ_PAGE_ADDR …
31 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX …
32 #define mmVGA_RENDER_CONTROL …
33 #define mmVGA_RENDER_CONTROL_BASE_IDX …
34 #define mmVGA_SEQUENCER_RESET_CONTROL …
35 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX …
36 #define mmVGA_MODE_CONTROL …
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| D | dcn_3_2_1_offset.h | 22 #define _dcn_3_2_1_OFFSET_HEADER
28 #define regDENTIST_DISPCLK_CNTL …
29 #define regDENTIST_DISPCLK_CNTL_BASE_IDX …
34 #define regPHYPLLA_PIXCLK_RESYNC_CNTL …
35 #define regPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX …
36 #define regPHYPLLB_PIXCLK_RESYNC_CNTL …
37 #define regPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX …
38 #define regPHYPLLC_PIXCLK_RESYNC_CNTL …
39 #define regPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX …
40 #define regPHYPLLD_PIXCLK_RESYNC_CNTL …
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_11_5_0_offset.h | 24 #define _gc_11_5_0_OFFSET_HEADER
30 #define regSDMA0_DEC_START …
31 #define regSDMA0_DEC_START_BASE_IDX …
32 #define regSDMA0_F32_MISC_CNTL …
33 #define regSDMA0_F32_MISC_CNTL_BASE_IDX …
34 #define regSDMA0_UCODE_VERSION …
35 #define regSDMA0_UCODE_VERSION_BASE_IDX …
36 #define regSDMA0_GLOBAL_TIMESTAMP_LO …
37 #define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX …
38 #define regSDMA0_GLOBAL_TIMESTAMP_HI …
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| D | gc_10_3_0_offset.h | 23 #define _gc_10_3_0_OFFSET_HEADER
25 #define mmSQ_DEBUG_STS_GLOBAL …
26 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX …
27 #define mmSQ_DEBUG_STS_GLOBAL2 …
28 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX …
29 #define mmSQ_DEBUG …
30 #define mmSQ_DEBUG_BASE_IDX …
34 #define mmSDMA0_DEC_START …
35 #define mmSDMA0_DEC_START_BASE_IDX …
36 #define mmSDMA0_GLOBAL_TIMESTAMP_LO …
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| D | gc_11_0_0_offset.h | 24 #define _gc_11_0_0_OFFSET_HEADER
30 #define regSDMA0_DEC_START …
31 #define regSDMA0_DEC_START_BASE_IDX …
32 #define regSDMA0_F32_MISC_CNTL …
33 #define regSDMA0_F32_MISC_CNTL_BASE_IDX …
34 #define regSDMA0_GLOBAL_TIMESTAMP_LO …
35 #define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX …
36 #define regSDMA0_GLOBAL_TIMESTAMP_HI …
37 #define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX …
38 #define regSDMA0_POWER_CNTL …
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| D | gc_9_4_2_offset.h | 24 #define _gc_9_4_2_OFFSET_HEADER
30 #define ixDIDT_SQ_CTRL0 …
31 #define ixDIDT_SQ_CTRL2 …
32 #define ixDIDT_SQ_STALL_CTRL …
33 #define ixDIDT_SQ_TUNING_CTRL …
34 #define ixDIDT_SQ_STALL_AUTO_RELEASE_CTRL …
35 #define ixDIDT_SQ_CTRL3 …
36 #define ixDIDT_SQ_STALL_PATTERN_1_2 …
37 #define ixDIDT_SQ_STALL_PATTERN_3_4 …
38 #define ixDIDT_SQ_STALL_PATTERN_5_6 …
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| D | gc_10_1_0_offset.h | 22 #define _gc_10_1_0_OFFSET_HEADER
24 #define mmSQ_DEBUG_STS_GLOBAL …
25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX …
26 #define mmSQ_DEBUG_STS_GLOBAL2 …
27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX …
31 #define mmSDMA0_DEC_START …
32 #define mmSDMA0_DEC_START_BASE_IDX …
33 #define mmSDMA0_PG_CNTL …
34 #define mmSDMA0_PG_CNTL_BASE_IDX …
35 #define mmSDMA0_PG_CTX_LO …
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| D | gc_9_2_1_offset.h | 22 #define _gc_9_2_1_OFFSET_HEADER
24 #define mmSQ_DEBUG_STS_GLOBAL …
25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX …
26 #define mmSQ_DEBUG_STS_GLOBAL2 …
27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX …
28 #define mmSQ_DEBUG_STS_GLOBAL3 …
29 #define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX …
33 #define mmGRBM_CNTL …
34 #define mmGRBM_CNTL_BASE_IDX …
35 #define mmGRBM_SKEW_CNTL …
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| D | gc_9_1_offset.h | 22 #define _gc_9_1_OFFSET_HEADER
24 #define mmSQ_DEBUG_STS_GLOBAL …
25 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX …
26 #define mmSQ_DEBUG_STS_GLOBAL2 …
27 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX …
28 #define mmSQ_DEBUG_STS_GLOBAL3 …
29 #define mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX …
33 #define mmGRBM_CNTL …
34 #define mmGRBM_CNTL_BASE_IDX …
35 #define mmGRBM_SKEW_CNTL …
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| D | gc_11_0_3_offset.h | 24 #define _gc_11_0_3_OFFSET_HEADER
30 #define regSDMA0_DEC_START …
31 #define regSDMA0_DEC_START_BASE_IDX …
32 #define regSDMA0_F32_MISC_CNTL …
33 #define regSDMA0_F32_MISC_CNTL_BASE_IDX …
34 #define regSDMA0_GLOBAL_TIMESTAMP_LO …
35 #define regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX …
36 #define regSDMA0_GLOBAL_TIMESTAMP_HI …
37 #define regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX …
38 #define regSDMA0_POWER_CNTL …
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
| D | mmhub_9_4_1_offset.h | 22 #define _mmhub_9_4_1_OFFSET_HEADER
28 #define mmDAGB0_RDCLI0 …
29 #define mmDAGB0_RDCLI0_BASE_IDX …
30 #define mmDAGB0_RDCLI1 …
31 #define mmDAGB0_RDCLI1_BASE_IDX …
32 #define mmDAGB0_RDCLI2 …
33 #define mmDAGB0_RDCLI2_BASE_IDX …
34 #define mmDAGB0_RDCLI3 …
35 #define mmDAGB0_RDCLI3_BASE_IDX …
36 #define mmDAGB0_RDCLI4 …
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| /linux-6.12.1/drivers/media/usb/dvb-usb/ |
| D | af9005.h | 12 #define _DVB_USB_AF9005_H_
14 #define DVB_USB_LOG_PREFIX "af9005"
18 #define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
19 #define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
20 #define deb_rc(args...) dprintk(dvb_usb_af9005_debug,0x04,args)
21 #define deb_reg(args...) dprintk(dvb_usb_af9005_debug,0x08,args)
22 #define deb_i2c(args...) dprintk(dvb_usb_af9005_debug,0x10,args)
23 #define deb_fw(args...) dprintk(dvb_usb_af9005_debug,0x20,args)
28 #define FW_BULKOUT_SIZE 250
36 #define AF9005_OFDM_REG 0
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/sdma/ |
| D | sdma_4_4_0_offset.h | 24 #define _sdma_4_4_0_OFFSET_HEADER
29 #define regSDMA0_UCODE_ADDR …
30 #define regSDMA0_UCODE_ADDR_BASE_IDX …
31 #define regSDMA0_UCODE_DATA …
32 #define regSDMA0_UCODE_DATA_BASE_IDX …
33 #define regSDMA0_VF_ENABLE …
34 #define regSDMA0_VF_ENABLE_BASE_IDX …
35 #define regSDMA0_CONTEXT_GROUP_BOUNDARY …
36 #define regSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX …
37 #define regSDMA0_POWER_CNTL …
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| /linux-6.12.1/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_7_1_sh_mask.h | 25 #define GMC_7_1_SH_MASK_H
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
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