| /linux-6.12.1/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,dcc.yaml | 4 $id: http://devicetree.org/schemas/soc/qcom/qcom,dcc.yaml#
13 DCC (Data Capture and Compare) is a DMA engine which is used to save
15 or SW trigger. DCC is used to capture and store data for debugging purpose
21 - qcom,sm8150-dcc
22 - qcom,sc7280-dcc
23 - qcom,sc7180-dcc
24 - qcom,sdm845-dcc
25 - const: qcom,dcc
29 - description: DCC base
30 - description: DCC RAM base
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | debugfs-driver-dcc | 1 What: /sys/kernel/debug/dcc/.../ready
5 This file is used to check the status of the dcc
7 A 'Y' here indicates dcc is ready.
9 What: /sys/kernel/debug/dcc/.../trigger
17 What: /sys/kernel/debug/dcc/.../config_reset
22 a dcc driver to the default configuration. When '1'
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
34 can be one of following dcc instructions: read,
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
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| /linux-6.12.1/drivers/tty/hvc/ |
| D | Kconfig | 81 bool "ARM JTAG DCC console"
86 This console uses the JTAG DCC on ARM to create a console under the HVC
91 bool "Use DCC only on CPU core 0"
95 Some external debuggers, do not handle reads/writes from/to DCC on more
96 than one CPU core. Each core has its own DCC device registers, so when a
97 CPU core reads or writes from/to DCC, it only accesses its own DCC device.
99 write to the console, it might write to a different DCC.
102 shows the DCC output only from that core's DCC. The result is that
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| D | hvc_dcc.c | 14 #include <asm/dcc.h>
19 /* DCC Status Bits */
26 /* Lock to serialize access to DCC fifo */
63 EARLYCON_DECLARE(dcc, dcc_early_console_setup);
93 * Check if the DCC is enabled. If CONFIG_HVC_DCC_SERIALIZE_SMP is enabled,
103 * If we're not on core 0, but we previously confirmed that DCC is in hvc_dcc_check()
129 * Workqueue function that writes the output FIFO to the DCC on core 0.
138 /* While there's data in the output FIFO, write it to the DCC */ in dcc_put_work()
155 * Workqueue function that reads characters from DCC and puts them into the
164 * Read characters from DCC and put them into the input FIFO, as in dcc_get_work()
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| /linux-6.12.1/net/netfilter/ |
| D | nf_conntrack_irc.c | 45 MODULE_DESCRIPTION("IRC (DCC) connection tracking helper");
53 MODULE_PARM_DESC(max_dcc_channels, "max number of expected DCC channels per "
56 MODULE_PARM_DESC(dcc_timeout, "timeout on for unestablished DCC channels");
64 /* tries to get the ip_addr and port out of a dcc command
66 * data pointer to first byte of DCC command data
67 * data_end pointer to last byte of dcc command data
68 * ip returns parsed ip of dcc command
69 * port returns parsed port of dcc command
175 /* strlen(" :\1DCC SENT t AAAAAAAA P\1\n")=26 in help()
186 /* then check that place only for the DCC command */ in help()
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| D | nf_nat_irc.c | 25 MODULE_DESCRIPTION("IRC (DCC) NAT helper");
58 /* strlen("\1DCC CHAT chat AAAAAAAA P\1\n")=27 in help()
59 * strlen("\1DCC SCHAT chat AAAAAAAA P\1\n")=28 in help()
60 * strlen("\1DCC SEND F AAAAAAAA P S\1\n")=26 in help()
61 * strlen("\1DCC MOVE F AAAAAAAA P S\1\n")=26 in help()
62 * strlen("\1DCC TSEND F AAAAAAAA P S\1\n")=27 in help()
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| /linux-6.12.1/fs/f2fs/ |
| D | segment.c | 953 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in __create_discard_cmd() local
959 pend_list = &dcc->pend_list[plist_idx(len)]; in __create_discard_cmd()
975 atomic_inc(&dcc->discard_cmd_cnt); in __create_discard_cmd()
976 dcc->undiscard_blks += len; in __create_discard_cmd()
984 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in f2fs_check_discard_tree() local
985 struct rb_node *cur = rb_first_cached(&dcc->root), *next; in f2fs_check_discard_tree()
1012 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in __lookup_discard_cmd() local
1013 struct rb_node *node = dcc->root.rb_root.rb_node; in __lookup_discard_cmd()
1086 static void __detach_discard_cmd(struct discard_cmd_control *dcc, in __detach_discard_cmd() argument
1090 atomic_sub(dc->queued, &dcc->queued_discard); in __detach_discard_cmd()
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| D | segment.h | 937 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in wake_up_discard_thread() local
944 mutex_lock(&dcc->cmd_lock); in wake_up_discard_thread()
946 if (i + 1 < dcc->discard_granularity) in wake_up_discard_thread()
948 if (!list_empty(&dcc->pend_list[i])) { in wake_up_discard_thread()
953 mutex_unlock(&dcc->cmd_lock); in wake_up_discard_thread()
957 dcc->discard_wake = true; in wake_up_discard_thread()
958 wake_up_interruptible_all(&dcc->discard_wait_queue); in wake_up_discard_thread()
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| /linux-6.12.1/Documentation/devicetree/bindings/serial/ |
| D | arm,dcc.yaml | 4 $id: http://devicetree.org/schemas/serial/arm,dcc.yaml#
7 title: ARM DCC (Data communication channel) serial emulation
13 ARM DCC (Data communication channel) serial emulation interface available
19 const: arm,dcc
29 compatible = "arm,dcc";
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| /linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_plane.c | 168 return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); in amdgpu_dm_plane_modifier_has_dcc()
256 /* for DCC we know it isn't rb aligned, so rb_per_se doesn't matter. */ in amdgpu_dm_plane_fill_gfx9_tiling_info_from_modifier()
264 const struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_validate_dcc() argument
275 if (!dcc->enable) in amdgpu_dm_plane_validate_dcc()
298 if (dcc->independent_64b_blks == 0 && in amdgpu_dm_plane_validate_dcc()
311 struct dc_plane_dcc_param *dcc, in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers() argument
326 dcc->enable = 1; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
327 dcc->meta_pitch = afb->base.pitches[1]; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
328 dcc->independent_64b_blks = independent_64b_blks; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
331 dcc->dcc_ind_blk = hubp_ind_block_64b_no_128bcl; in amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn30/ |
| D | dcn30_hubp.c | 351 struct dc_plane_dcc_param *dcc) in hubp3_dcc_control_sienna_cichlid() argument
356 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
357 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
358 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c, in hubp3_dcc_control_sienna_cichlid()
359 SECONDARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
360 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
361 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c); in hubp3_dcc_control_sienna_cichlid()
401 struct dc_plane_dcc_param *dcc, in hubp3_program_surface_config() argument
407 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp3_program_surface_config()
409 hubp2_program_size(hubp, format, plane_size, dcc); in hubp3_program_surface_config()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| D | dcn201_hubp.c | 48 struct dc_plane_dcc_param *dcc, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
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| /linux-6.12.1/drivers/bus/ |
| D | vexpress-config.c | 108 u32 *position, u32 *dcc) in vexpress_config_get_topo() argument
116 vexpress_config_find_prop(node, "arm,vexpress,dcc", dcc); in vexpress_config_get_topo()
257 u32 site, position, dcc; in vexpress_syscfg_regmap_init() local
261 &position, &dcc); in vexpress_syscfg_regmap_init()
301 func, site, position, dcc, in vexpress_syscfg_regmap_init()
304 func->template[i] = SYS_CFGCTRL_DCC(dcc); in vexpress_syscfg_regmap_init()
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| /linux-6.12.1/arch/arm/boot/dts/arm/ |
| D | vexpress-v2p-ca5s.dts | 144 dcc {
202 temp-dcc {
203 /* DCC internal operating temperature */
206 label = "DCC";
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| D | vexpress-v2p-ca15-tc1.dts | 141 dcc {
217 temp-dcc {
218 /* DCC internal temperature */
221 label = "DCC";
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| /linux-6.12.1/arch/arm64/include/asm/ |
| D | dcc.h | 6 * not speculative read the DCC status before executing the read or write
10 * and instead reads the DCC register every time.
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| D | dml21_translation_helper.c | 613 surface->dcc.enable = false; in populate_dml21_dummy_surface_cfg()
614 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_dummy_surface_cfg()
615 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_dummy_surface_cfg()
616 surface->dcc.informative.fraction_of_zero_size_request_plane0 = 0; in populate_dml21_dummy_surface_cfg()
617 surface->dcc.informative.fraction_of_zero_size_request_plane1 = 0; in populate_dml21_dummy_surface_cfg()
679 surface->dcc.enable = plane_state->dcc.enable; in populate_dml21_surface_config_from_plane_state()
680 surface->dcc.informative.dcc_rate_plane0 = 1.0; in populate_dml21_surface_config_from_plane_state()
681 surface->dcc.informative.dcc_rate_plane1 = 1.0; in populate_dml21_surface_config_from_plane_state()
682 …surface->dcc.informative.fraction_of_zero_size_request_plane0 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
683 …surface->dcc.informative.fraction_of_zero_size_request_plane1 = plane_state->dcc.independent_64b_b… in populate_dml21_surface_config_from_plane_state()
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| /linux-6.12.1/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp-zcu1275-revA.dts | 22 serial1 = &dcc;
37 &dcc {
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| D | zynqmp-zc1254-revA.dts | 22 serial1 = &dcc;
37 &dcc {
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| D | zynqmp-zc1232-revA.dts | 21 serial1 = &dcc;
36 &dcc {
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn35/ |
| D | dcn35_hubp.c | 178 struct dc_plane_dcc_param *dcc, in hubp35_program_surface_config() argument
184 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp35_program_surface_config()
186 hubp2_program_size(hubp, format, plane_size, dcc); in hubp35_program_surface_config()
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-gic-realview.c | 62 /* new irq mode with no DCC */ in realview_gic_of_init()
69 pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); in realview_gic_of_init()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn401/ |
| D | dcn401_hubp.c | 512 struct dc_plane_dcc_param *dcc) in hubp401_dcc_control() argument
517 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp401_dcc_control()
518 SECONDARY_SURFACE_DCC_EN, dcc->enable); in hubp401_dcc_control()
538 struct dc_plane_dcc_param *dcc) in hubp401_program_size() argument
574 struct dc_plane_dcc_param *dcc, in hubp401_program_surface_config() argument
580 hubp401_dcc_control(hubp, dcc); in hubp401_program_surface_config()
582 hubp401_program_size(hubp, format, plane_size, dcc); in hubp401_program_surface_config()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| D | dcn10_hubp.c | 167 struct dc_plane_dcc_param *dcc) in hubp1_program_size() argument
180 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
182 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp1_program_size()
185 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
190 if (!dcc->enable) { in hubp1_program_size()
541 struct dc_plane_dcc_param *dcc, in hubp1_program_surface_config() argument
545 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp1_program_surface_config()
547 hubp1_program_size(hubp, format, plane_size, dcc); in hubp1_program_surface_config()
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| /linux-6.12.1/drivers/gpu/drm/i915/gt/ |
| D | intel_ggtt_fencing.c | 668 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle() local
672 * determined by DCC. For single-channel, neither the CPU in detect_bit_6_swizzle()
679 switch (dcc & DCC_ADDRESSING_MODE_MASK) { in detect_bit_6_swizzle()
686 if (dcc & DCC_CHANNEL_XOR_DISABLE) { in detect_bit_6_swizzle()
693 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { in detect_bit_6_swizzle()
712 if (dcc == 0xffffffff) { in detect_bit_6_swizzle()
|