| /linux-6.12.1/Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ad5755.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD5755 Multi-Channel DAC
10 - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
15 - adi,ad5755
16 - adi,ad5755-1
17 - adi,ad5757
18 - adi,ad5735
19 - adi,ad5737
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| D | dcn31_dccg.c | 35 (dccg_dcn->regs->reg)
39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
42 dccg_dcn->base.ctx
44 dccg->ctx->logger
50 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg31_update_dpp_dto()
58 if (dccg->ref_dppclk && req_dppclk) { in dccg31_update_dpp_dto()
59 int ref_dppclk = dccg->ref_dppclk; in dccg31_update_dpp_dto()
60 int modulo, phase; in dccg31_update_dpp_dto() local
62 // phase / modulo = dpp pipe clk / dpp global clk in dccg31_update_dpp_dto()
64 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg31_update_dpp_dto()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn35/ |
| D | dcn35_dccg.c | 1 /* SPDX-License-Identifier: MIT */
34 (dccg_dcn->regs->reg)
38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
41 dccg_dcn->base.ctx
43 dccg->ctx->logger
140 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && enable) in dccg35_set_dsc_clk_rcg()
169 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable) in dccg35_set_symclk32_se_rcg()
208 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable) in dccg35_set_symclk32_le_rcg()
235 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable) in dccg35_set_physymclk_rcg()
272 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable) in dccg35_set_symclk_fe_rcg()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn401/ |
| D | dcn401_dccg.c | 44 (dccg_dcn->regs->reg)
48 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
51 dccg_dcn->base.ctx
53 dccg->ctx->logger
81 if (dccg->ref_dppclk && req_dppclk) { in dccg401_update_dpp_dto()
82 int ref_dppclk = dccg->ref_dppclk; in dccg401_update_dpp_dto()
83 int modulo, phase; in dccg401_update_dpp_dto() local
85 // phase / modulo = dpp pipe clk / dpp global clk in dccg401_update_dpp_dto()
87 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg401_update_dpp_dto()
89 if (phase > 0xff) { in dccg401_update_dpp_dto()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 2 * Copyright 2020-2021 Advanced Micro Devices, Inc.
37 optc1->tg_regs->reg
40 optc1->base.ctx
44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
186 double ratio, modulo, phase; in optc3_fpu_set_vrr_m_const() local
193 * VOTAL_MAX - VTOTAL_MIN = 1 in optc3_fpu_set_vrr_m_const()
201 * of lines in a frame - 1'. in optc3_fpu_set_vrr_m_const()
213 optc->funcs->set_vtotal_min_max(optc, 0, 0); in optc3_fpu_set_vrr_m_const()
223 ratio = vtotal_max - vtotal_avg; in optc3_fpu_set_vrr_m_const()
224 modulo = 65536.0 * 65536.0 - 1.0; /* 2^32 - 1 */ in optc3_fpu_set_vrr_m_const()
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| /linux-6.12.1/Documentation/devicetree/bindings/ |
| D | trivial-devices.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
[all …]
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| /linux-6.12.1/drivers/regulator/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
64 the netlink mechanism. User-space applications can subscribe to these events
65 for real-time updates on various regulator events.
75 They provide two I2C-controlled DC/DC step-down converters with
101 tristate "Active-semi act8865 voltage regulator"
106 This driver controls a active-semi act8865 voltage output
110 tristate "Active-semi ACT8945A voltage regulator"
113 This driver controls a active-semi ACT8945A voltage regulator
114 via I2C bus. The ACT8945A features three step-down DC/DC converters
[all …]
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| /linux-6.12.1/drivers/tty/ |
| D | nozomi.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * nozomi.c -- HSDPA driver Broadband Wireless Data Card - Globe Trotter
18 * --------------------------------------------------------------------------
25 * --------------------------------------------------------------------------
132 F32_2 = 2048, /* 512 bytes downlink + uplink * 2 -> 2048 */
133 F32_8 = 8192, /* 3072 bytes downl. + 1024 bytes uplink * 2 -> 8192 */
157 CTRL_ERROR = -1,
167 PORT_ERROR = -1,
176 * else A-channels must always be used.
184 /* Is for now only needed during initialization phase */
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| /linux-6.12.1/Documentation/gpu/amdgpu/display/ |
| D | index.rst | 1 .. _amdgpu-display-core:
4 drm/amd/display - Display Core (DC)
10 #. **Display Core (DC)** contains the OS-agnostic components. Things like
12 #. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
16 ------------------
17 DC Code validation
18 ------------------
22 DC case, we maintain a tree to centralize code from different parts. The shared
29 the prefix **DC Patches for <DATE>**, which is created based on the latest
30 `amd-staging-drm-next <https://gitlab.freedesktop.org/agd5f/linux>`_. All of
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml/dcn401/ |
| D | dcn401_fpu.c | 1 // SPDX-License-Identifier: MIT
16 double pstate_latency_us = clk_mgr->ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn401_build_wm_range_table_fpu()
17 double fclk_change_latency_us = clk_mgr->ctx->dc->dml.soc.fclk_change_latency_us; in dcn401_build_wm_range_table_fpu()
18 double sr_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_exit_time_us; in dcn401_build_wm_range_table_fpu()
19 double sr_enter_plus_exit_time_us = clk_mgr->ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn401_build_wm_range_table_fpu()
21 uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz; in dcn401_build_wm_range_table_fpu()
22 uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
24 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz; in dcn401_build_wm_range_table_fpu()
30 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_secon… in dcn401_build_wm_range_table_fpu()
32 …clk_mgr->bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->bw_params->clk_… in dcn401_build_wm_range_table_fpu()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| D | dcn401_dpp_dscl.c | 44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
67 /* Autocal calculate the scaling ratio and initial phase and the
103 return -1; /* Unsupported */ in dpp401_dscl_get_pixel_depth_val()
132 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp401_dscl_get_dscl_mode()
134 if (data->format == PIXEL_FORMAT_FP16) in dpp401_dscl_get_dscl_mode()
138 if (data->ratios.horz.value == one in dpp401_dscl_get_dscl_mode()
139 && data->ratios.vert.value == one in dpp401_dscl_get_dscl_mode()
140 && data->ratios.horz_c.value == one in dpp401_dscl_get_dscl_mode()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/regulator/ |
| D | dlg,da9210.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Dialog Semiconductor DA9210 Multi-Phase 12A DC-DC Buck Converter
10 - Support Opensource <support.opensource@diasemi.com>
13 - $ref: regulator.yaml#
26 - compatible
27 - reg
32 - |
33 #include <dt-bindings/interrupt-controller/irq.h>
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| D | dcn10_dpp_dscl.c | 44 dpp->tf_regs->reg
47 dpp->base.ctx
51 dpp->tf_shift->field_name, dpp->tf_mask->field_name
65 /* Autocal calculate the scaling ratio and initial phase and the
101 return -1; /* Unsupported */ in dpp1_dscl_get_pixel_depth_val()
130 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
132 if (data->format == PIXEL_FORMAT_FP16) in dpp1_dscl_get_dscl_mode()
136 if (data->ratios.horz.value == one in dpp1_dscl_get_dscl_mode()
137 && data->ratios.vert.value == one in dpp1_dscl_get_dscl_mode()
138 && data->ratios.horz_c.value == one in dpp1_dscl_get_dscl_mode()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
| D | dcn10_hwseq.c | 67 hws->ctx
69 hws->regs->reg
73 hws->shifts->field_name, hws->masks->field_name
88 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
97 void dcn10_lock_all_pipes(struct dc *dc, in dcn10_lock_all_pipes() argument
106 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
107 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
108 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes()
109 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
115 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clock_source.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
42 (clk_src->regs->reg)
45 clk_src->base.ctx
48 calc_pll_cs->ctx->logger
50 struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll
54 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
76 ss_parm = clk_src->dvi_ss_params; in get_ss_data_entry()
77 entrys_num = clk_src->dvi_ss_params_cnt; in get_ss_data_entry()
81 ss_parm = clk_src->hdmi_ss_params; in get_ss_data_entry()
82 entrys_num = clk_src->hdmi_ss_params_cnt; in get_ss_data_entry()
[all …]
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| /linux-6.12.1/drivers/iio/dac/ |
| D | ad5755.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
128 * struct ad5755_platform_data - AD5755 DAC driver platform data
129 * @ext_dc_dc_compenstation_resistor: Whether an external DC-DC converter
131 * @dc_dc_phase: DC-DC converter phase.
132 * @dc_dc_freq: DC-DC converter frequency.
133 * @dc_dc_maxv: DC-DC maximum allowed boost voltage.
162 * struct ad5755_chip_info - chip specific information
174 * struct ad5755_state - driver instance specific data
257 st->data[0].d32 = cpu_to_be32((reg << 16) | val); in ad5755_write_unlocked()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| D | dcn314_dccg.c | 1 // SPDX-License-Identifier: MIT
37 (dccg_dcn->regs->reg)
41 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
44 dccg_dcn->base.ctx
46 dccg->ctx->logger
204 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
211 int req_dtbclk_khz = params->pixclk_khz / 4; in dccg314_set_dtbclk_dto()
213 if (params->ref_dtbclk_khz && req_dtbclk_khz) { in dccg314_set_dtbclk_dto()
214 uint32_t modulo, phase; in dccg314_set_dtbclk_dto() local
216 // phase / modulo = dtbclk / dtbclk ref in dccg314_set_dtbclk_dto()
[all …]
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| /linux-6.12.1/drivers/hwmon/pmbus/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
37 be called acbel-fsg032.
55 ADM1293, and ADM1294 Hot-Swap Controller and Digital Power Monitors.
77 be called bel-pfe.
80 tristate "BluTek BPA-RS600 Power Supplies"
83 BPA-RS600 Power Supplies.
86 be called bpa-rs600.
89 tristate "Delta AHE-50DC fan control module"
92 the integrated fan control module of the Delta AHE-50DC
96 will be called delta-ahe50dc-fan.
[all …]
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| D | delta-ahe50dc-fan.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Delta AHE-50DC power shelf fan control module driver
29 return value == PMBUS_CLEAR_FAULTS ? -EOPNOTSUPP : -ENODATA; in ahe50dc_fan_write_byte()
32 static int ahe50dc_fan_read_word_data(struct i2c_client *client, int page, int phase, int reg) in ahe50dc_fan_read_word_data() argument
34 /* temp1 in (virtual) page 1 is remapped to mfr-specific temp4 */ in ahe50dc_fan_read_word_data()
38 return -EOPNOTSUPP; in ahe50dc_fan_read_word_data()
62 return -ENODATA; in ahe50dc_fan_read_word_data()
64 return -EOPNOTSUPP; in ahe50dc_fan_read_word_data()
101 client->dev.platform_data = &ahe50dc_fan_data; in ahe50dc_fan_probe()
112 { .compatible = "delta,ahe50dc-fan" },
[all …]
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| /linux-6.12.1/Documentation/hwmon/ |
| D | ucd9200.rst | 11 Addresses scanned: -
15 - http://focus.ti.com/lit/ds/symlink/ucd9220.pdf
16 - http://focus.ti.com/lit/ds/symlink/ucd9222.pdf
17 - http://focus.ti.com/lit/ds/symlink/ucd9224.pdf
18 - http://focus.ti.com/lit/ds/symlink/ucd9240.pdf
19 - http://focus.ti.com/lit/ds/symlink/ucd9244.pdf
20 - http://focus.ti.com/lit/ds/symlink/ucd9246.pdf
21 - http://focus.ti.com/lit/ds/symlink/ucd9248.pdf
23 Author: Guenter Roeck <linux@roeck-us.net>
27 -----------
[all …]
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| D | ltc2978.rst | 10 Addresses scanned: -
18 Addresses scanned: -
26 Addresses scanned: -
34 Addresses scanned: -
42 Addresses scanned: -
52 Addresses scanned: -
60 Addresses scanned: -
68 Addresses scanned: -
76 Addresses scanned: -
84 Addresses scanned: -
[all …]
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| D | xdpe12284.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -----------
27 This driver implements support for Infineon Multi-phase XDPE112 and XDPE122
32 - Intel VR13 and VR13HC rev 1.3, IMVP8 rev 1.2 and IMPVP9 rev 1.3 DC-DC
34 - Intel SVID rev 1.9. protocol.
35 - PMBus rev 1.3 interface.
41 - VR12.0 mode, 5-mV DAC - 0x01.
42 - VR12.5 mode, 10-mV DAC - 0x02.
43 - IMVP9 mode, 5-mV DAC - 0x03.
44 - AMD mode 6.25mV - 0x10.
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/ |
| D | dml2_wrapper.c | 1 /* SPDX-License-Identifier: MIT */
37 static void initialize_dml2_ip_params(struct dml2_context *dml2, const struct dc *in_dc, struct ip_… in initialize_dml2_ip_params()
39 if (dml2->config.use_native_soc_bb_construction) in initialize_dml2_ip_params()
45 static void initialize_dml2_soc_bbox(struct dml2_context *dml2, const struct dc *in_dc, struct soc_… in initialize_dml2_soc_bbox()
47 if (dml2->config.use_native_soc_bb_construction) in initialize_dml2_soc_bbox()
54 const struct dc *in_dc, const struct soc_bounding_box_st *in_bbox, struct soc_states_st *out) in initialize_dml2_soc_states()
56 if (dml2->config.use_native_soc_bb_construction) in initialize_dml2_soc_states()
59 dml2_translate_soc_states(in_dc, out, in_dc->dml.soc.num_states); in initialize_dml2_soc_states()
69 in_out_display_cfg->hw.ODMMode[i] = mode_support_info->ODMMode[i]; in map_hw_resources()
70 in_out_display_cfg->hw.DPPPerSurface[i] = mode_support_info->DPPPerSurface[i]; in map_hw_resources()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_dp_training_dpia.c | 30 #include "dc.h"
44 link->ctx->logger
66 DPIA_TS_UFP_DONE = 0xff /* Done training DPTX-to-DPIA hop. */
95 * @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis).
106 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", in dpia_configure_link()
108 link->link_id.enum_id - ENUM_ID_1, in dpia_configure_link()
109 lt_settings->lttpr_mode); in dpia_configure_link()
116 dp_get_lttpr_mode_override(link, <_settings->lttpr_mode); in dpia_configure_link()
119 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
124 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/display/ |
| D | solomon,ssd1307fb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Ripard <mripard@kernel.org>
11 - Javier Martinez Canillas <javierm@redhat.com>
17 - enum:
18 - solomon,ssd1305fb-i2c
19 - solomon,ssd1306fb-i2c
20 - solomon,ssd1307fb-i2c
21 - solomon,ssd1309fb-i2c
[all …]
|