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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Drenesas,rzv2m-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2M Clocked Serial Interface (CSI)
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 - $ref: spi-controller.yaml#
18 const: renesas,rzv2m-csi
28 - description: The clock used to generate the output clock (CSICLK)
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/linux-6.12.1/drivers/spi/
Dspi-rzv2m-csi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Renesas RZ/V2M Clocked Serial Interface (CSI) driver
22 #define CSI_MODE 0x00 /* CSI mode control */
23 #define CSI_CLKSEL 0x04 /* CSI clock select */
24 #define CSI_CNT 0x08 /* CSI control */
25 #define CSI_INT 0x0C /* CSI interrupt status */
26 #define CSI_IFIFOL 0x10 /* CSI receive FIFO level display */
27 #define CSI_OFIFOL 0x14 /* CSI transmit FIFO level display */
28 #define CSI_IFIFO 0x18 /* CSI receive window */
29 #define CSI_OFIFO 0x1C /* CSI transmit window */
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/linux-6.12.1/drivers/clk/sunxi-ng/
Dccu-sun8i-a83t.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
22 #include "ccu-sun8i-a83t.h"
29 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
44 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
92 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
97 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
109 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
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Dccu-sun8i-a33.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
37 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
50 * can no longer be used, as the audio codec requests the exact clock
52 * variable divider to 1. This means the clock rates will no longer
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
84 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
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Dccu-sun9i-a80.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
79 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
84 /* Some PLLs are input * N / div1 / div2. Model them as NKMP with no K */
95 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
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Dccu-sun5i.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
34 .hw.init = CLK_HW_INIT("pll-core",
46 * With sigma-delta modulation for fractional-N on the audio PLL,
48 * can no longer be used, as the audio codec requests the exact clock
50 * variable divider to 1. This means the clock rates will no longer
74 .hw.init = CLK_HW_INIT("pll-audio-base",
91 .hw.init = CLK_HW_INIT("pll-video0",
106 .hw.init = CLK_HW_INIT("pll-ve",
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Dccu-sun6i-a31.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * Based on ccu-sun8i-h3.c by Maxime Ripard.
10 #include <linux/clk-provider.h>
30 #include "ccu-sun6i-a31.h"
32 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
46 * With sigma-delta modulation for fractional-N on the audio PLL,
48 * can no longer be used, as the audio codec requests the exact clock
50 * variable divider to 1. This means the clock rates will no longer
[all …]
Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
28 #include "ccu-sun4i-a10.h"
38 .hw.init = CLK_HW_INIT("pll-core",
50 * With sigma-delta modulation for fractional-N on the audio PLL,
52 * can no longer be used, as the audio codec requests the exact clock
54 * variable divider to 1. This means the clock rates will no longer
73 .hw.init = CLK_HW_INIT("pll-audio-base",
91 .hw.init = CLK_HW_INIT("pll-video0",
106 .hw.init = CLK_HW_INIT("pll-ve",
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8x-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 stdout-path = &lpuart3;
11 colibri_gpio_keys: gpio-keys {
12 compatible = "gpio-keys";
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_gpiokeys>;
17 key-wakeup {
18 debounce-interval = <10>;
20 label = "Wake-Up";
22 wakeup-source;
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Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
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Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
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/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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/linux-6.12.1/drivers/net/wireless/realtek/rtw89/
Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
45 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
102 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
103 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
251 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
252 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
253 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
696 /* HE DCM only support 1ss and 2ss */
750 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
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Dphy.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
19 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy0_phy1_offset()
21 return phy->phy0_phy1_offset(rtwdev, addr); in rtw89_phy0_phy1_offset()
27 u32 bit_rate = report->bit_rate; in get_max_amsdu_len()
34 if (report->might_fallback_legacy) in get_max_amsdu_len()
37 /* lower than 20M vht 2ss mcs8, make it small */ in get_max_amsdu_len()
41 /* lower than 40M vht 2ss mcs9, make it medium */ in get_max_amsdu_len()
45 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ in get_max_amsdu_len()
49 return rtwdev->chip->max_amsdu_limit; in get_max_amsdu_len()
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