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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dspear_spics.txt1 === ST Microelectronics SPEAr SPI CS Driver ===
13 the control of this interface as gpio.
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
[all …]
/linux-6.12.1/arch/arm64/boot/dts/exynos/
Dexynosautov920-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov920 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov920 SoC pin-mux and pin-config options are listed as
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include "exynos-pinctrl.h"
16 gpa0: gpa0-gpio-bank {
17 gpio-controller;
18 #gpio-cells = <2>;
19 interrupt-controller;
20 #interrupt-cells = <2>;
[all …]
Dexynosautov9-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's ExynosAutov9 SoC pin-mux and pin-config device tree source
7 * Samsung's ExynosAutov9 SoC pin-mux and pin-config options are listed as
11 #include "exynos-pinctrl.h"
14 gpa0: gpa0-gpio-bank {
15 gpio-controller;
16 #gpio-cells = <2>;
17 interrupt-controller;
18 #interrupt-cells = <2>;
19 interrupt-parent = <&gic>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/exynos/google/
Dgs101-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * GS101 SoC pin-mux and pin-config device tree source
5 * Copyright 2019-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 #include "gs101-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
15 interrupt-controller;
16 #interrupt-cells = <2>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
[all …]
Dbrcm,bcm2835-aux-spi.txt8 - compatible: Should be "brcm,bcm2835-aux-spi".
9 - reg: Should contain register location and length for the spi block
10 - interrupts: Should contain shared interrupt of the aux block
11 - clocks: The clock feeding the SPI controller - needs to
15 - cs-gpios: the cs-gpios (native cs is NOT supported)
16 see also spi-bus.txt
21 compatible = "brcm,bcm2835-aux-spi";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>;
[all …]
Dspi-davinci.txt4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
Dsamsung,spi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - enum:
20 - google,gs101-spi
21 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
22 - samsung,s3c6410-spi
23 - samsung,s5pv210-spi # for S5PV210 and S5PC110
24 - samsung,exynos4210-spi
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
24 mpp0 0 gpio, nand(io2), spi(cs)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
31 mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig)
[all …]
/linux-6.12.1/drivers/mtd/nand/raw/atmel/
Dnand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
23 * Derived from Das U-Boot source code
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
38 * - atmel_nand_: all generic structures/functions
39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
45 * - <soc>_nand_: all SoC specific structures/functions
49 #include <linux/dma-mapping.h>
[all …]
/linux-6.12.1/arch/riscv/boot/dts/canaan/
Dsipeed_maix_dock.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-dock-m1", "sipeed,maix-dock-m1w",
18 "canaan,kendryte-k210";
26 stdout-path = "serial0:115200n8";
29 gpio-leds {
[all …]
Dcanaan_kd233.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210";
24 stdout-path = "serial0:115200n8";
27 gpio-leds {
28 compatible = "gpio-leds";
39 gpio-keys {
[all …]
Dsipeed_maix_bit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-bit", "sipeed,maix-bitm",
18 "canaan,kendryte-k210";
26 stdout-path = "serial0:115200n8";
29 gpio-leds {
[all …]
Dsipeed_maix_go.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-go", "canaan,kendryte-k210";
25 stdout-path = "serial0:115200n8";
28 gpio-leds {
29 compatible = "gpio-leds";
[all …]
Dsipeed_maixduino.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "sipeed,maixduino", "canaan,kendryte-k210";
24 stdout-path = "serial0:115200n8";
27 gpio-keys {
28 compatible = "gpio-keys";
30 key-boot {
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dstm32mp15xx-dhcor-drc-compact.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
21 stdout-path = "serial0:115200n8";
25 compatible = "gpio-leds";
29 default-state = "off";
35 default-state = "off";
40 compatible = "regulator-fixed";
41 regulator-name = "vio";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 gpio = <&gpioh 2 GPIO_ACTIVE_LOW>;
[all …]
Dstm32mp15xx-dhcom-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
6 #include "stm32mp15-pinctrl.dtsi"
7 #include "stm32mp15xxaa-pinctrl.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/mfd/st,stpmic1.h>
24 reserved-memory {
25 #address-cells = <1>;
26 #size-cells = <1>;
30 compatible = "shared-dma-pool";
[all …]
/linux-6.12.1/drivers/gpio/
Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
3 * OF helpers for the GPIO API
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
22 #include <linux/gpio/consumer.h>
23 #include <linux/gpio/machine.h>
26 #include "gpiolib-of.h"
29 * This is Linux-specific flags. By default controllers' and Linux' mapping
30 * match, but GPIO controllers are free to translate their own flags to
31 * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
44 * of_gpio_named_count() - Count GPIOs for a device
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsc7280-idp-ec-h1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
15 compatible = "google,cros-ec-spi";
17 interrupt-parent = <&tlmm>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&ap_ec_int_l>;
21 spi-max-frequency = <3000000>;
22 wakeup-source;
25 compatible = "google,cros-ec-pwm";
[all …]
/linux-6.12.1/arch/m68k/include/asm/
Dm525xsim.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
55 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
56 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
57 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
58 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
59 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
60 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
61 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
62 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
[all …]
/linux-6.12.1/Documentation/iio/
Dad4000.rst1 .. SPDX-License-Identifier: GPL-2.0-only
30 ------------------
35 CS mode, 3-wire turbo mode
38 Datasheet "3-wire" mode is what most resembles standard SPI connection which,
39 for these devices, comprises of connecting the controller CS line to device CNV
41 "CS Mode, 3-Wire Turbo Mode" connection in datasheets.
42 NOTE: The datasheet definition of 3-wire mode for the AD4000 series is NOT the
43 same of standard spi-3wire mode.
47 Omit the ``adi,sdi-pin`` property in device tree to select this mode.
51 +-------------+
[all …]
/linux-6.12.1/arch/mips/boot/dts/cavium-octeon/
Docteon_3xxx.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
7 compatible = "cavium,octeon-3860";
8 #address-cells = <2>;
9 #size-cells = <2>;
10 interrupt-parent = <&ciu>;
13 compatible = "simple-bus";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 ciu: interrupt-controller@1070000000000 {
[all …]
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dat91-sama5d3_eds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet
10 /dts-v1/;
15 compatible = "microchip,sama5d3-eds", "atmel,sama5d36",
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_key_gpio>;
28 button-3 {
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7944.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <Michael.Hennerich@analog.com>
11 - Nuno Sá <nuno.sa@analog.com>
14 A family of pin-compatible single channel differential analog to digital
21 $ref: /schemas/spi/spi-peripheral-props.yaml#
26 - adi,ad7944
27 - adi,ad7985
28 - adi,ad7986
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dti,gpmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
[all …]

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