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/linux-6.12.1/Documentation/devicetree/bindings/chrome/
Dgoogle,cros-ec-typec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/chrome/google,cros-ec-typec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Google Chrome OS EC(Embedded Controller) Type C port driver.
10 - Benson Leung <bleung@chromium.org>
11 - Prashant Malani <pmalani@chromium.org>
14 Chrome OS devices have an Embedded Controller(EC) which has access to
17 cros-ec node like google,cros-ec-spi.
21 const: google,cros-ec-typec
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/linux-6.12.1/Documentation/devicetree/bindings/mfd/
Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Guenter Roeck <groeck@chromium.org>
14 Google's ChromeOS EC is a microcontroller which talks to the AP and
16 The EC can be connected through various interfaces (I2C, SPI, and others)
22 - description:
23 For implementations of the EC connected through I2C.
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/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsc7280-idp-ec-h1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 EC/H1 over SPI (common between IDP2 and CRD)
11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
14 cros_ec: ec@0 {
15 compatible = "google,cros-ec-spi";
17 interrupt-parent = <&tlmm>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&ap_ec_int_l>;
21 spi-max-frequency = <3000000>;
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Dsc7280-herobrine.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
16 #include <dt-bindings/input/gpio-keys.h>
17 #include <dt-bindings/input/input.h>
18 #include <dt-bindings/leds/common.h>
20 #include "sc7280-qcard.dtsi"
21 #include "sc7280-chrome-common.dtsi"
25 stdout-path = "serial0:115200n8";
38 ppvar_sys: ppvar-sys-regulator {
39 compatible = "regulator-fixed";
40 regulator-name = "ppvar_sys";
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Dsc7180-trogdor.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/sc7180-lpass.h>
16 #include "sc7180-firmware-tfa.dtsi"
22 thermal-zones {
23 charger_thermal: charger-thermal {
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/linux-6.12.1/drivers/platform/chrome/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # tell define_trace.h where to find the cros ec trace header
4 CFLAGS_cros_ec_trace.o:= -I$(src)
5 CFLAGS_cros_ec_sensorhub_ring.o:= -I$(src)
7 obj-$(CONFIG_CHROMEOS_ACPI) += chromeos_acpi.o
8 obj-$(CONFIG_CHROMEOS_LAPTOP) += chromeos_laptop.o
9 obj-$(CONFIG_CHROMEOS_PRIVACY_SCREEN) += chromeos_privacy_screen.o
10 obj-$(CONFIG_CHROMEOS_PSTORE) += chromeos_pstore.o
11 obj-$(CONFIG_CHROMEOS_TBMC) += chromeos_tbmc.o
12 obj-$(CONFIG_CROS_EC) += cros_ec.o
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Dcros_ec_typec.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Chrome OS EC.
22 #define DRV_NAME "cros-ec-typec"
33 switch_fwnode = fwnode_find_reference(fwnode, "usb-role-switch", 0); in cros_typec_role_switch_quirk()
37 if (adev && !adev->pld_crc) in cros_typec_role_switch_quirk()
38 adev->pld_crc = to_acpi_device_node(fwnode)->pld_crc; in cros_typec_role_switch_quirk()
52 ret = fwnode_property_read_string(fwnode, "power-role", &buf); in cros_typec_parse_port_props()
54 dev_err(dev, "power-role not found: %d\n", ret); in cros_typec_parse_port_props()
61 cap->type = ret; in cros_typec_parse_port_props()
63 ret = fwnode_property_read_string(fwnode, "data-role", &buf); in cros_typec_parse_port_props()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
26 If you have an ACPI-compatible Chromebook, say Y or M here.
47 The range of memory used is 0xf00000-0x1000000, traditionally
70 Controller (EC) providing keyboard, battery and power services.
72 protocol for talking to the EC is defined by the bus driver.
83 EC through an I2C bus. This uses a simple byte-level protocol with
91 If you say Y here, you get support for talking to the ChromeOS EC
92 through rpmsg. This uses a simple byte-level protocol with a
93 checksum. Also since there's no addition EC-to-host interrupt, this
104 If you say Y here, you get support for talking to the ChromeOS EC
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Dcros_typec_switch.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * This driver provides the ability to configure Type-C muxes and retimers which are controlled by
6 * the ChromeOS EC.
29 /* Driver-specific data. */
32 struct cros_ec_device *ec; member
48 return cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_CONTROL, &req, sizeof(req), NULL, 0); in cros_typec_cmd_mux_set()
53 int ret = -EOPNOTSUPP; in cros_typec_get_mux_state()
60 } else if (alt && alt->svid == USB_TYPEC_DP_SID) { in cros_typec_get_mux_state()
62 pin_assign = mode - TYPEC_STATE_MODAL; in cros_typec_get_mux_state()
79 return cros_ec_cmd(sdata->ec, 0, EC_CMD_TYPEC_CONTROL, &req, sizeof(req), NULL, 0); in cros_typec_send_clear_event()
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/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
21 stdout-path = "serial0:115200n8";
25 compatible = "pwm-backlight";
27 power-supply = <&reg_vsys>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
31 default-brightness-level = <576>;
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Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
32 power-supply = <&ppvar_sys>;
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Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
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Dmt8186-corsola.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
7 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
26 stdout-path = "serial0:115200n8";
35 backlight_lcd0: backlight-lcd0 {
36 compatible = "pwm-backlight";
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/linux-6.12.1/drivers/mfd/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
57 tristate "Active-semi ACT8945A"
62 Support for the ACT8945A PMIC from Active-semi. This device
63 features three step-down DC/DC converters and four low-dropout
79 sun4i-gpadc-iio and the hwmon driver iio_hwmon.
82 called sun4i-gpadc.
113 tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down
144 over at91-usart-serial driver and usart-spi-driver. Only one function
160 tristate "Atmel HLCDC (High-end LCD Controller)"
197 tristate "X-Powers AC100"
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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