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/linux-6.12.1/drivers/clk/nxp/
Dclk-lpc18xx-creg.c38 #define CREG_CLK(_name, _emask, _ops) \ macro
132 [CREG_CLK_1KHZ] = CREG_CLK("1khz_clk", EN1KHZ, clk_creg_1k),
133 [CREG_CLK_32KHZ] = CREG_CLK("32khz_clk", EN32KHZ, clk_creg_32k),
137 struct clk_creg_data *creg_clk, in clk_register_creg_clk() argument
143 init.ops = creg_clk->ops; in clk_register_creg_clk()
144 init.name = creg_clk->name; in clk_register_creg_clk()
149 creg_clk->reg = syscon; in clk_register_creg_clk()
150 creg_clk->hw.init = &init; in clk_register_creg_clk()
153 return devm_clk_register(dev, &creg_clk->hw); in clk_register_creg_clk()
155 return clk_register(NULL, &creg_clk->hw); in clk_register_creg_clk()
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dlpc1850-creg-clk.txt37 creg_clk: clock-controller {
48 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
Dlpc1850-cgu.txt120 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
/linux-6.12.1/Documentation/devicetree/bindings/rtc/
Dnxp,lpc1788-rtc.yaml55 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/
Dlpc18xx.dtsi204 creg_clk: clock-controller { label
228 clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
236 clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;