Home
last modified time | relevance | path

Searched +full:cpu +full:- +full:bpmp +full:- +full:tx (Results 1 – 10 of 10) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The BPMP is a specific processor in Tegra chip, which is designed for
16 management, and reset control tasks from the CPU. The binding document
17 defines the resources that would be used by the BPMP firmware driver,
[all …]
Dnvidia,tegra210-bpmp.txt1 NVIDIA Tegra210 Boot and Power Management Processor (BPMP)
3 The Boot and Power Management Processor (BPMP) is a co-processor found
8 be used by the BPMP T210 firmware driver, which can create the
9 interprocessor communication (IPC) between the CPU and BPMP.
12 - compatible
15 - "nvidia,tegra210-bpmp"
16 - reg: physical base address and length for HW synchornization primitives
19 - interrupts: specifies the interrupt number for receiving messages ("rx")
20 and for triggering messages ("tx")
23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
[all …]
/linux-6.12.1/drivers/cpufreq/
Dtegra186-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
12 #include <soc/tegra/bpmp.h>
13 #include <soc/tegra/bpmp-abi.h>
28 /* CPU0 - A57 Cluster */
33 /* CPU1 - Denver Cluster */
38 /* CPU2 - Denver Cluster */
43 /* CPU3 - A57 Cluster */
48 /* CPU4 - A57 Cluster */
53 /* CPU5 - A57 Cluster */
[all …]
Dtegra194-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved
6 #include <linux/cpu.h>
8 #include <linux/dma-mapping.h>
18 #include <soc/tegra/bpmp.h>
19 #include <soc/tegra/bpmp-abi.h>
30 #define CORE_OFFSET(cpu) (cpu * 8) argument
32 #define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu)) argument
36 (data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base))
37 #define CORE_ACTMON_CNTR_REG(data, cl, cpu) (CLUSTER_ACTMON_BASE(data, cl) + CORE_OFFSET(cpu)) argument
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/linux-6.12.1/drivers/i2c/busses/
Di2c-tegra-bpmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/i2c/busses/i2c-tegra-bpmp.c
19 #include <soc/tegra/bpmp-abi.h>
20 #include <soc/tegra/bpmp.h>
32 struct tegra_bpmp *bpmp; member
37 * Linux flags are translated to BPMP defined I2C flags that are used in BPMP
70 * [addr little-endian][flags little-endian][len little-endian][data if write]
71 * [addr little-endian][flags little-endian][len little-endian][data if write]
87 char *buf = request->xfer.data_buf; in tegra_bpmp_serialize_i2c_msg()
94 tegra_bpmp_xlate_flags(msg->flags, &flags); in tegra_bpmp_serialize_i2c_msg()
[all …]
/linux-6.12.1/include/soc/tegra/
Dbpmp-abi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
44 * @brief Messages sent to/from BPMP via IPC
56 * The CPU requests the BPMP to perform a particular service by
61 * The BPMP processes the data and replies with an IVC frame (on the
66 * A well-defined subset of the MRQ messages that the CPU sends to the
67 * BPMP can lead to BPMP eventually sending an MRQ message to the
68 * CPU. For example, when the CPU uses an #MRQ_THERMAL message to set
69 * a thermal trip point, the BPMP may eventually send a single
70 * #MRQ_THERMAL message of its own to the CPU indicating that the trip
[all …]
/linux-6.12.1/include/dt-bindings/clock/
Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
382 /** @brief NAFLL clock source for BPMP */
518 /** @brief NAFLL clock source for CPU cluster 0 */
521 /** @brief NAFLL clock source for CPU cluster 1 */
524 /** @brief NAFLL clock source for CPU cluster 2 */
633 /** @brief ungated version of TX symbol clock after fixed 1/2 divider */
801 /** @brief NAFLL clock source for CPU cluster 0 DSUCLK */
804 /** @brief NAFLL clock source for CPU cluster 1 DSUCLK */
807 /** @brief NAFLL clock source for CPU cluster 2 DSUCLK */