| /linux-6.12.1/Documentation/devicetree/bindings/arm/ |
| D | arm,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Snoop Control Unit (SCU)
10 - Linus Walleij <linus.walleij@linaro.org>
13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
22 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
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| /linux-6.12.1/arch/arm/boot/dts/arm/ |
| D | vexpress-v2p-ca9.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A9 MPCore (V2P-CA9)
8 * HBI-0191B
11 /dts-v1/;
12 #include "vexpress-v2m.dtsi"
15 model = "V2P-CA9";
18 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
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| D | arm-realview-pbx-a9.dts | 23 /dts-v1/;
24 #include "arm-realview-pbx.dtsi"
28 * This is the RealView Platform Baseboard Explore for Cortex-A9
31 model = "ARM RealView Platform Baseboard Explore for Cortex-A9";
35 #address-cells = <1>;
36 #size-cells = <0>;
37 enable-method = "arm,realview-smp";
39 cpu-map {
51 compatible = "arm,cortex-a9";
53 next-level-cache = <&L2>;
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| D | vexpress-v2p-ca5s.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A5 MPCore (V2P-CA5s)
8 * HBI-0225B
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA5s";
18 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <1>;
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| /linux-6.12.1/arch/arm/mach-bcm/ |
| D | bcm63xx_smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 /* Size of mapped Cortex A9 SCU address space */
26 * Enable the Cortex A9 Snoop Control Unit
29 * cores present. We assume we're running on a Cortex A9 processor,
31 * SCU base is a problem.
43 return -ENXIO; in scu_a9_enable()
50 return -ENOENT; in scu_a9_enable()
55 pr_err("failed to remap config base (%lu/%u) for SCU\n", in scu_a9_enable()
57 return -ENOMEM; in scu_a9_enable()
70 /* The BCM63138 SoC has two Cortex-A9 CPUs, CPU0 features a complete in scu_a9_enable()
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| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
12 #include <linux/irqchip/irq-bcm2836.h>
27 /* Size of mapped Cortex A9 SCU address space */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
38 * Enable the Cortex A9 Snoop Control Unit
41 * cores present. We assume we're running on a Cortex A9 processor,
43 * SCU base is a problem.
54 return -ENXIO; in scu_a9_enable()
61 return -ENOENT; in scu_a9_enable()
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/ux500/ |
| D | boards.txt | 1 ST-Ericsson Ux500 boards
2 ------------------------
5 compatible = "st-ericsson,mop500" (legacy)
6 compatible = "st-ericsson,u8500"
10 soc: represents the system-on-chip and contains the chip
20 compatible = "ste,dbx500-backupram"
22 scu:
23 see binding for arm/arm,scu.yaml
25 interrupt-controller:
26 see binding for interrupt-controller/arm,gic.txt
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| /linux-6.12.1/arch/arm/mach-versatile/ |
| D | platsmp-realview.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 * The ARM11MP SCU compatible is only provided as fallback for
23 * old RealView EB Cortex-A9 device trees that were using this
26 { .compatible = "arm,arm11mp-scu", },
27 { .compatible = "arm,cortex-a9-scu", },
28 { .compatible = "arm,cortex-a5-scu", },
33 { .compatible = "arm,core-module-integrator", },
34 { .compatible = "arm,realview-eb-syscon", },
35 { .compatible = "arm,realview-pbx-syscon", },
49 pr_err("PLATSMP: No SCU base address\n"); in realview_smp_prepare_cpus()
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| D | platsmp-vexpress.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 * The best way to detect a multi-cluster configuration in vexpress_smp_init_ops()
40 cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); in vexpress_smp_init_ops()
57 { .compatible = "arm,cortex-a5-scu", },
58 { .compatible = "arm,cortex-a9-scu", },
64 struct device_node *scu = of_find_matching_node(NULL, in vexpress_smp_dt_prepare_cpus() local
67 if (scu) in vexpress_smp_dt_prepare_cpus()
68 scu_enable(of_iomap(scu, 0)); in vexpress_smp_dt_prepare_cpus()
72 * system-wide flags register. The boot monitor waits in vexpress_smp_dt_prepare_cpus()
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| /linux-6.12.1/arch/arm/boot/dts/broadcom/ |
| D | bcm63138.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&gic>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a9";
28 next-level-cache = <&L2>;
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| D | bcm-ns.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
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| /linux-6.12.1/arch/arm/boot/dts/actions/ |
| D | owl-s500.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (c) 2016-2017 Andreas Färber
8 #include <dt-bindings/clock/actions,s500-cmu.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/owl-s500-powergate.h>
12 #include <dt-bindings/reset/actions,s500-reset.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | nuvoton,npcm750-smp | 2 Secondary CPU enable-method "nuvoton,npcm750-smp" binding
5 To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
8 Enable method name: "nuvoton,npcm750-smp"
10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
15 "nuvoton,npcm750-gcr".
20 #address-cells = <1>;
21 #size-cells = <0>;
22 enable-method = "nuvoton,npcm750-smp";
26 compatible = "arm,cortex-a9";
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| D | marvell,berlin-smp | 2 Secondary CPU enable-method "marvell,berlin-smp" binding
5 This document describes the "marvell,berlin-smp" method for enabling secondary
6 CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should
9 Enable method name: "marvell,berlin-smp"
11 Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9"
15 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
16 "marvell,berlin-cpu-ctrl"[1].
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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| /linux-6.12.1/arch/arm/kernel/ |
| D | smp_scu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
27 * Get the number of CPU cores from the SCU configuration
36 * Enable the SCU
43 /* Cortex-A9 only */ in scu_enable()
58 /* Cortex-A9 earlier than r2p0 has no standby bit in SCU */ in scu_enable()
66 * Ensure that the data accessed by CPU0 before the SCU was in scu_enable()
81 return -EINVAL; in scu_set_power_mode_internal()
118 return -EINVAL; in scu_get_cpu_power_mode()
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| /linux-6.12.1/arch/arm/boot/dts/axis/ |
| D | artpec6.dtsi | 2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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| /linux-6.12.1/arch/arm/mach-npcm/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt
28 gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr"); in npcm7xx_smp_boot_secondary()
31 ret = -ENODEV; in npcm7xx_smp_boot_secondary()
37 ret = -ENOMEM; in npcm7xx_smp_boot_secondary()
57 scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in npcm7xx_smp_prepare_cpus()
59 pr_err("no scu device node\n"); in npcm7xx_smp_prepare_cpus()
64 pr_err("could not iomap scu"); in npcm7xx_smp_prepare_cpus()
78 CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm750-smp", &npcm7xx_smp_ops);
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| /linux-6.12.1/arch/arm/boot/dts/synaptics/ |
| D | berlin2q.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
6 #include <dt-bindings/clock/berlin2q.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 model = "Marvell Armada 1500 pro (BG2-Q) SoC";
12 #address-cells = <1>;
13 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
23 enable-method = "marvell,berlin-smp";
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| /linux-6.12.1/arch/arm/mach-ux500/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2009 ST-Ericsson.
36 np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram"); in ux500_smp_prepare_cpus()
48 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in ux500_smp_prepare_cpus()
50 pr_err("No SCU base address\n"); in ux500_smp_prepare_cpus()
56 pr_err("No SCU remap\n"); in ux500_smp_prepare_cpus()
100 CPU_METHOD_OF_DECLARE(ux500_smp, "ste,dbx500-smp", &ux500_smp_ops);
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| /linux-6.12.1/arch/arm/boot/dts/marvell/ |
| D | armada-375.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
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| D | armada-39x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
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| /linux-6.12.1/arch/arm/boot/dts/amlogic/ |
| D | meson8.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 #include <dt-bindings/clock/meson8-ddr-clkc.h>
7 #include <dt-bindings/clock/meson8b-clkc.h>
8 #include <dt-bindings/gpio/meson8-gpio.h>
9 #include <dt-bindings/power/meson8-power.h>
10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
20 #address-cells = <1>;
21 #size-cells = <0>;
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| /linux-6.12.1/arch/arm/mach-actions/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <linux/soc/actions/owl-sps.h>
45 return -EINVAL; in s500_wakeup_secondary()
69 timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); in s500_wakeup_secondary()
71 timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); in s500_wakeup_secondary()
91 writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4); in s500_smp_boot_secondary()
92 writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4); in s500_smp_boot_secondary()
101 node = of_find_compatible_node(NULL, NULL, "actions,s500-timer"); in s500_smp_prepare_cpus()
113 node = of_find_compatible_node(NULL, NULL, "actions,s500-sps"); in s500_smp_prepare_cpus()
126 node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in s500_smp_prepare_cpus()
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| /linux-6.12.1/arch/arm/mach-socfpga/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2010-2011 Calxeda, Inc.
23 int trampoline_size = secondary_trampoline_end - secondary_trampoline; in socfpga_boot_secondary()
48 int trampoline_size = secondary_trampoline_end - secondary_trampoline; in socfpga_a10_boot_secondary()
74 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); in socfpga_smp_prepare_cpus()
76 pr_err("%s: missing scu\n", __func__); in socfpga_smp_prepare_cpus()
88 * platform-specific code to shutdown a CPU
129 CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
130 CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", &socfpga_a10_smp_ops);
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| /linux-6.12.1/arch/arm/boot/dts/rockchip/ |
| D | rk3xxx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
37 compatible = "fixed-clock";
38 clock-frequency = <24000000>;
39 #clock-cells = <0>;
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