| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-cti | 1 What: /sys/bus/coresight/devices/<cti-name>/enable
5 Description: (RW) Enable/Disable the CTI hardware.
7 What: /sys/bus/coresight/devices/<cti-name>/powered
11 Description: (Read) Indicate if the CTI hardware is powered.
13 What: /sys/bus/coresight/devices/<cti-name>/ctmid
19 What: /sys/bus/coresight/devices/<cti-name>/nr_trigger_cons
23 Description: (Read) Number of devices connected to triggers on this CTI
25 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/name
31 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_signals
37 What: /sys/bus/coresight/devices/<cti-name>/triggers<N>/in_types
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-cti.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph.
17 The CTI component properties define the connections between the individual
18 CTI and the components it is directly connected to, consisting of input and
[all …]
|
| /linux-6.12.1/arch/arm64/boot/dts/hisilicon/ |
| D | hi6220-coresight.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * dtsi file for Hisilicon Hi6220 coresight
14 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
17 clock-names = "apb_pclk";
19 out-ports {
22 remote-endpoint =
28 in-ports {
31 remote-endpoint =
39 compatible = "arm,coresight-tmc", "arm,primecell";
42 clock-names = "apb_pclk";
[all …]
|
| /linux-6.12.1/Documentation/trace/coresight/ |
| D | coresight-ect.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight Embedded Cross Trigger (CTI & CTM).
11 --------------------
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
[all …]
|
| D | coresight.rst | 2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
[all …]
|
| D | coresight-config.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight System Configuration Manager
13 The CoreSight System Configuration manager is an API that allows the
14 programming of the CoreSight system with pre-defined configurations that
17 Many CoreSight components can be programmed in complex ways - especially ETMs.
18 In addition, components can interact across the CoreSight system, often via
19 the cross trigger components such as CTI and CTM. These system settings can
26 This section introduces the basic concepts of a CoreSight system configuration.
30 --------
32 A feature is a named set of programming for a CoreSight device. The programming
[all …]
|
| /linux-6.12.1/drivers/hwtracing/coresight/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for CoreSight drivers.
7 subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter
8 subdir-ccflags-y += -Wmissing-declarations
9 subdir-ccflags-y += -Wmissing-format-attribute
10 subdir-ccflags-y += -Wmissing-prototypes
11 subdir-ccflags-y += -Wold-style-definition
12 subdir-ccflags-y += -Wmissing-include-dirs
13 subdir-ccflags-y += -Wno-sign-compare
15 $(call cc-option, -Wrestrict) \
[all …]
|
| D | coresight-cti.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/coresight.h>
18 #include "coresight-priv.h"
22 * 0x000 - 0x144: CTI programming and status
23 * 0xEDC - 0xEF8: CTI integration test.
24 * 0xF00 - 0xFFC: Coresight management registers.
26 /* CTI programming registers */
41 #define ITCHINACK 0xEDC /* WO CTI CSSoc 400 only*/
42 #define ITTRIGINACK 0xEE0 /* WO CTI CSSoc 400 only*/
43 #define ITCHOUT 0xEE4 /* WO RW-600 */
[all …]
|
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
13 This framework provides a kernel interface for the CoreSight debug
15 a topological view of the CoreSight components based on a DT
20 module will be called coresight.
22 if CORESIGHT
24 tristate "CoreSight Link and Sink drivers"
26 This enables support for CoreSight link and sink drivers that are
[all …]
|
| D | coresight-cti-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/coresight.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
17 /* Number of CTI signals in the v8 architecturally defined connection */
22 /* CTI device tree trigger connection node keyword */
23 #define CTI_DT_CONNS "trig-conns"
25 /* CTI device tree connection property keywords */
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
[all …]
|
| D | coresight-cti-core.c | 1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/coresight.h>
22 #include "coresight-priv.h"
23 #include "coresight-cti.h"
26 * CTI devices can be associated with a PE, or be connected to CoreSight
30 * We assume that the non-CPU CTIs are always powered as we do with sinks etc.
36 /* net of CTI devices connected via CTM */
43 dev_get_drvdata(csdev->dev.parent)
52 * CTI naming. CTI bound to cores will have the name cti_cpu<N> where
56 * CTI device name list - for CTI not bound to cores.
[all …]
|
| D | coresight-config.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/coresight.h>
13 /* CoreSight Configuration Management - component and system wide configuration */
28 * system configuration - used by config data and devices.
33 /* flags defining device instance matching - used in config match desc data. */
40 * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c
66 * @hw_info: optional hardware device type specific information. (ETM / CTI specific etc)
69 * @mask32: 32 bit mask when using 32 bit value to access device register - if mask type.
89 * Device feature descriptor - combination of registers and parameters to
117 * Configuration descriptor - describes selectable system configuration.
[all …]
|
| D | coresight-cti-sysfs.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight.h>
15 #include "coresight-cti.h"
25 * include\dt-bindings\arm\coresight-cti-dt.h
85 struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); in enable_show()
87 spin_lock(&drvdata->spinlock); in enable_show()
88 enable_req = drvdata->config.enable_req_count; in enable_show()
89 powered = drvdata->config.hw_powered; in enable_show()
90 enabled = drvdata->config.hw_enabled; in enable_show()
91 spin_unlock(&drvdata->spinlock); in enable_show()
[all …]
|
| /linux-6.12.1/arch/arm64/boot/dts/arm/ |
| D | juno-base.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 clock-frequency = <50000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
19 frame-number = <1>;
31 #mbox-cells = <1>;
33 clock-names = "apb_pclk";
[all …]
|
| D | juno-cs-r1r2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
8 clock-names = "apb_pclk";
9 power-domains = <&scpi_devpd 0>;
10 out-ports {
13 remote-endpoint = <&etf1_in_port>;
17 in-ports {
27 compatible = "arm,coresight-tmc", "arm,primecell";
31 clock-names = "apb_pclk";
32 power-domains = <&scpi_devpd 0>;
[all …]
|
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
[all …]
|
| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
[all …]
|
| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
13 #include "juno-base.dtsi"
14 #include "juno-cs-r1r2.dtsi"
18 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
28 stdout-path = "serial0:115200n8";
[all …]
|
| /linux-6.12.1/arch/arm/include/asm/ |
| D | cti.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/hardware/coresight.h>
35 * CoreSight v1.0 Architecture Specification
41 * struct cti - cross trigger interface struct
42 * @base: mapped virtual address for the cti base
43 * @irq: irq number for the cti
47 * cti struct used to operate cti registers.
49 struct cti { struct
56 * cti_init - initialize the cti instance argument
57 * @cti: cti instance
[all …]
|
| /linux-6.12.1/arch/arm64/boot/dts/qcom/ |
| D | sm6115.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
14 #include <dt-bindings/interconnect/qcom,sm6115.h>
[all …]
|
| D | msm8916.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/soc/qcom,apr.h>
[all …]
|
| D | sa8775p.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interconnect/qcom,icc.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
10 #include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
11 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
12 #include <dt-bindings/mailbox/qcom-ipcc.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/power/qcom,rpmhpd.h>
[all …]
|
| /linux-6.12.1/include/dt-bindings/arm/ |
| D | coresight-cti-dt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * types on CoreSight CTI.
|
| /linux-6.12.1/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]
|