Searched +full:copro +full:- +full:sw +full:- +full:interrupts (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/misc/aspeed,ast2400-cvic.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Andrew Jeffery <andrew@codeconstruct.com.au>13 The Aspeed AST2400 and AST2500 SoCs have a controller that provides interrupts24 - enum:25 - aspeed,ast2400-cvic26 - aspeed,ast2500-cvic27 - const: aspeed,cvic[all …]
1 // SPDX-License-Identifier: GPL-2.0+25 #include "fsi-master.h"26 #include "cf-fsi-fw.h"28 #define FW_FILE_NAME "cf-fsi-fw.bin"132 msg->msg <<= bits; in msg_push_bits()133 msg->msg |= data & ((1ull << bits) - 1); in msg_push_bits()134 msg->bits += bits; in msg_push_bits()142 top = msg->bits & 0x3; in msg_push_crc()144 /* start bit, and any non-aligned top bits */ in msg_push_crc()145 crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1); in msg_push_crc()[all …]
1 // SPDX-License-Identifier: GPL-2.0+2 #include <dt-bindings/clock/aspeed-clock.h>3 #include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>8 #address-cells = <1>;9 #size-cells = <1>;10 interrupt-parent = <&vic>;36 #address-cells = <1>;37 #size-cells = <0>;40 compatible = "arm,arm1176jzf-s";52 compatible = "simple-bus";[all …]