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/linux-6.12.1/arch/mips/mm/
Dsc-mips.c122 unsigned int config2 = read_c0_config2(); in mips_sc_is_activated() local
137 if (config2 & (1 << 12)) in mips_sc_is_activated()
141 tmp = (config2 >> 4) & 0x0f; in mips_sc_is_activated()
186 unsigned int config1, config2; in mips_sc_probe() local
202 /* Does this MIPS32/MIPS64 CPU have a config2 register? */ in mips_sc_probe()
207 config2 = read_c0_config2(); in mips_sc_probe()
212 tmp = (config2 >> 8) & 0x0f; in mips_sc_probe()
218 tmp = (config2 >> 0) & 0x0f; in mips_sc_probe()
227 * According to config2 it would be 5-ways, but that is in mips_sc_probe()
236 * According to config2 it would be 5-ways and 512-sets, in mips_sc_probe()
Dc-r4k.c1357 unsigned int config2, lsize; in probe_vcache() local
1362 config2 = read_c0_config2(); in probe_vcache()
1363 if ((lsize = ((config2 >> 20) & 15))) in probe_vcache()
1368 c->vcache.sets = 64 << ((config2 >> 24) & 15); in probe_vcache()
1369 c->vcache.ways = 1 + ((config2 >> 16) & 15); in probe_vcache()
1460 unsigned int config2, lsize; in loongson3_sc_init() local
1462 config2 = read_c0_config2(); in loongson3_sc_init()
1463 lsize = (config2 >> 4) & 15; in loongson3_sc_init()
1468 c->scache.sets = 64 << ((config2 >> 8) & 15); in loongson3_sc_init()
1469 c->scache.ways = 1 + (config2 & 15); in loongson3_sc_init()
/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-bus-event_source-devices-iommu7 perf_event_attr.config1 or perf_event_attr.config2 for
13 or perf_event_attr.config2. All supported attributes
27 filter_pasid = "config2:0-21" - PASID filter
28 filter_ats = "config2:24-28" - Address Type filter
29 filter_page_table = "config2:32-36" - Page Table Level filter
/linux-6.12.1/drivers/staging/iio/addac/
Dadt7316.c100 * ADT7316 config2
185 u8 config2; member
318 if (chip->config2 & ADT7316_AD_SINGLE_CH_MODE) in adt7316_show_mode()
331 u8 config2; in adt7316_store_mode() local
334 config2 = chip->config2 & (~ADT7316_AD_SINGLE_CH_MODE); in adt7316_store_mode()
336 config2 |= ADT7316_AD_SINGLE_CH_MODE; in adt7316_store_mode()
338 ret = chip->bus.write(chip->bus.client, ADT7316_CONFIG2, config2); in adt7316_store_mode()
342 chip->config2 = config2; in adt7316_store_mode()
368 if (!(chip->config2 & ADT7316_AD_SINGLE_CH_MODE)) in adt7316_show_ad_channel()
371 switch (chip->config2 & ADT7516_AD_SINGLE_CH_MASK) { in adt7316_show_ad_channel()
[all …]
/linux-6.12.1/drivers/perf/amlogic/
Dmeson_ddr_pmu_core.c122 u64 config2 = event->attr.config2; in meson_ddr_perf_event_init() local
135 hweight64(config1) + hweight64(config2) > MAX_AXI_PORTS_OF_CHANNEL) in meson_ddr_perf_event_init()
154 u64 config2 = event->attr.config2; in meson_ddr_perf_event_add() local
163 (const unsigned long *)&config2, in meson_ddr_perf_event_add()
164 BITS_PER_TYPE(config2)) in meson_ddr_perf_event_add()
307 if (sscanf(value, "config2:%d", &id) == 1) in meson_ddr_perf_format_attr_visible()
/linux-6.12.1/tools/perf/tests/
Dpmu.c58 { "krava21", "config2:0-3,10-13,20-23,30-33,40-43,50-53,60-63\n", }, in test_pmu_get()
59 { "krava22", "config2:8,18,48,58\n", }, in test_pmu_get()
60 { "krava23", "config2:28-29,38\n", }, in test_pmu_get()
193 if (attr.config2 != 0x0400000020041d07) { in test__pmu_format()
194 pr_err("Unexpected config2 value %llx\n", attr.config2); in test__pmu_format()
244 if (attr->config2 != 0x0400000020041d07) { in test__pmu_events()
245 pr_err("Unexpected config2 value %llx\n", attr->config2); in test__pmu_events()
/linux-6.12.1/drivers/mtd/nand/raw/
Dmxc_nand.c145 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
446 * complete by checking the INT bit of config2 register.
692 uint32_t config2; in mxc_nand_enable_hwecc_v3() local
697 config2 = readl(NFC_V3_CONFIG2); in mxc_nand_enable_hwecc_v3()
700 config2 |= NFC_V3_CONFIG2_ECC_EN; in mxc_nand_enable_hwecc_v3()
702 config2 &= ~NFC_V3_CONFIG2_ECC_EN; in mxc_nand_enable_hwecc_v3()
704 writel(config2, NFC_V3_CONFIG2); in mxc_nand_enable_hwecc_v3()
1153 uint32_t config2, config3; in preset_v3() local
1169 config2 = NFC_V3_CONFIG2_ONE_CYCLE | in preset_v3()
1179 config2 |= NFC_V3_CONFIG2_PS_2048; in preset_v3()
[all …]
/linux-6.12.1/drivers/net/ethernet/seeq/
Dether3.c176 ether3_outw(priv(dev)->regs.config2 |= CFG2_CTRLO, REG_CONFIG2); in ether3_ledoff()
187 if (priv(dev)->regs.config2 & CFG2_CTRLO) in ether3_ledon()
188 ether3_outw(priv(dev)->regs.config2 &= ~CFG2_CTRLO, REG_CONFIG2); in ether3_ledon()
274 priv(dev)->regs.config2 = CFG2_CTRLO|CFG2_RECVCRC|CFG2_ERRENCRC; in ether3_init_2()
301 ether3_outw(priv(dev)->regs.config2, REG_CONFIG2); in ether3_init_2()
337 priv(dev)->regs.config2 |= CFG2_CTRLO; in ether3_init_for_open()
345 ether3_outw(priv(dev)->regs.config2, REG_CONFIG2); in ether3_init_for_open()
471 priv(dev)->regs.config2 |= CFG2_CTRLO; in ether3_timeout()
473 ether3_outw(priv(dev)->regs.config2, REG_CONFIG2); in ether3_timeout()
850 ether3_outw(priv(dev)->regs.config2 |= CFG2_CTRLO, REG_CONFIG2); in ether3_remove()
/linux-6.12.1/arch/x86/events/intel/
Duncore_nhmex.c199 DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63");
374 reg2->config = event->attr.config2; in nhmex_bbox_hw_config()
459 reg2->config = event->attr.config2; in nhmex_sbox_hw_config()
808 if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN) in nhmex_mbox_hw_config()
809 reg2->config = event->attr.config2; in nhmex_mbox_hw_config()
872 DEFINE_UNCORE_FORMAT_ATTR(filter_cfg_en, filter_cfg_en, "config2:63");
873 DEFINE_UNCORE_FORMAT_ATTR(filter_match, filter_match, "config2:0-33");
874 DEFINE_UNCORE_FORMAT_ATTR(filter_mask, filter_mask, "config2:34-61");
1027 er->config2 == reg2->config)) { in nhmex_rbox_get_constraint()
1031 er->config2 = reg2->config; in nhmex_rbox_get_constraint()
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra124-apalis-emc.dtsi318 nvidia,emc-auto-cal-config2 = <0x00000000>;
415 nvidia,emc-auto-cal-config2 = <0x00000000>;
512 nvidia,emc-auto-cal-config2 = <0x00000000>;
609 nvidia,emc-auto-cal-config2 = <0x00000000>;
706 nvidia,emc-auto-cal-config2 = <0x00000000>;
803 nvidia,emc-auto-cal-config2 = <0x00000000>;
900 nvidia,emc-auto-cal-config2 = <0x00000000>;
997 nvidia,emc-auto-cal-config2 = <0x00000000>;
1094 nvidia,emc-auto-cal-config2 = <0x00000000>;
1191 nvidia,emc-auto-cal-config2 = <0x00000000>;
[all …]
Dtegra124-jetson-tk1-emc.dtsi422 nvidia,emc-auto-cal-config2 = <0x00000000>;
590 nvidia,emc-auto-cal-config2 = <0x00000000>;
758 nvidia,emc-auto-cal-config2 = <0x00000000>;
926 nvidia,emc-auto-cal-config2 = <0x00000000>;
1094 nvidia,emc-auto-cal-config2 = <0x00000000>;
1262 nvidia,emc-auto-cal-config2 = <0x00000000>;
1430 nvidia,emc-auto-cal-config2 = <0x00000000>;
1598 nvidia,emc-auto-cal-config2 = <0x00000000>;
1766 nvidia,emc-auto-cal-config2 = <0x00000000>;
1934 nvidia,emc-auto-cal-config2 = <0x00000000>;
[all …]
Dtegra124-nyan-blaze-emc.dtsi384 nvidia,emc-auto-cal-config2 = <0x00000000>;
552 nvidia,emc-auto-cal-config2 = <0x00000000>;
720 nvidia,emc-auto-cal-config2 = <0x00000000>;
888 nvidia,emc-auto-cal-config2 = <0x00000000>;
1056 nvidia,emc-auto-cal-config2 = <0x00000000>;
1224 nvidia,emc-auto-cal-config2 = <0x00000000>;
1392 nvidia,emc-auto-cal-config2 = <0x00000000>;
1560 nvidia,emc-auto-cal-config2 = <0x00000000>;
1728 nvidia,emc-auto-cal-config2 = <0x00000000>;
1896 nvidia,emc-auto-cal-config2 = <0x00000000>;
/linux-6.12.1/drivers/mmc/host/
Dau1xmmc.c198 u32 config2; in SEND_STOP() local
203 config2 = __raw_readl(HOST_CONFIG2(host)); in SEND_STOP()
204 __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); in SEND_STOP()
744 u32 config2; in au1xmmc_set_ios() local
757 config2 = __raw_readl(HOST_CONFIG2(host)); in au1xmmc_set_ios()
760 config2 |= SD_CONFIG2_BB; in au1xmmc_set_ios()
763 config2 &= ~SD_CONFIG2_BB; in au1xmmc_set_ios()
764 config2 |= SD_CONFIG2_WB; in au1xmmc_set_ios()
767 config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB); in au1xmmc_set_ios()
770 __raw_writel(config2, HOST_CONFIG2(host)); in au1xmmc_set_ios()
/linux-6.12.1/drivers/iommu/intel/
Dperfmon.c84 IOMMU_PMU_ATTR(filter_pasid, "config2:0-21", IOMMU_PMU_FILTER_PASID);
85 IOMMU_PMU_ATTR(filter_ats, "config2:24-28", IOMMU_PMU_FILTER_ATS);
86 IOMMU_PMU_ATTR(filter_page_table, "config2:32-36", IOMMU_PMU_FILTER_PAGE_TABLE);
422 iommu_pmu_set_filter(pasid, event->attr.config2, in iommu_pmu_assign_event()
425 iommu_pmu_set_filter(ats, event->attr.config2, in iommu_pmu_assign_event()
428 iommu_pmu_set_filter(page_table, event->attr.config2, in iommu_pmu_assign_event()
/linux-6.12.1/tools/perf/arch/x86/tests/
Dhybrid.c155 TEST_ASSERT_VAL("wrong config2", 3 == evsel->core.attr.config2); in test__checkevent_pmu()
227 .name = "cpu_core/config=10,config1,config2=3,period=1000/u",
/linux-6.12.1/drivers/scsi/
Dmac53c94.h38 unsigned char config2; member
185 * Bits in config2 register.
Dam53c974.c229 if (esp->config2 & ESP_CONFIG2_FENAB) in pci_esp_send_dma_cmd()
252 if (esp->config2 & ESP_CONFIG2_FENAB) in pci_esp_dma_length_limit()
421 esp->config2 |= ESP_CONFIG2_FENAB; in pci_esp_probe_one()
/linux-6.12.1/tools/perf/tests/attr/
Dbase-record-spe37 config2=*
Dbase-stat38 config2=0
Dbase-record38 config2=0
Dtest-record-dummy-C052 config2=0
Dsystem-wide-dummy49 config2=0
/linux-6.12.1/arch/mips/kernel/
Dcpu-probe.c490 unsigned int config2; in decode_config2() local
492 config2 = read_c0_config2(); in decode_config2()
494 if (config2 & MIPS_CONF2_SL) in decode_config2()
497 return config2 & MIPS_CONF_M; in decode_config2()
866 unsigned int config2; in decode_guest_config2() local
868 probe_gc0_config(config2, config2, MIPS_CONF_M); in decode_guest_config2()
870 if (config2 & MIPS_CONF_M) in decode_guest_config2()
872 return config2 & MIPS_CONF_M; in decode_guest_config2()
1752 * XBurst misses a config2 register, so config3 decode was skipped in in cpu_probe_ingenic()
/linux-6.12.1/drivers/hwtracing/coresight/
Dcoresight-etm-perf.c68 PMU_FORMAT_ATTR(sinkid, "config2:0-31");
70 PMU_FORMAT_ATTR(configid, "config2:32-63");
332 if (event->attr.config2 & GENMASK_ULL(31, 0)) { in etm_setup_aux()
333 id = (u32)event->attr.config2; in etm_setup_aux()
338 cfg_hash = (u32)((event->attr.config2 & GENMASK_ULL(63, 32)) >> 32); in etm_setup_aux()
/linux-6.12.1/drivers/perf/
Darm_dmc620_pmu.c179 #define ATTR_CFG_FLD_invert_CFG config2
182 #define ATTR_CFG_FLD_incr_CFG config2
185 #define ATTR_CFG_FLD_event_CFG config2
188 #define ATTR_CFG_FLD_clkdiv2_CFG config2

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