| /linux-6.12.1/drivers/tty/serial/ |
| D | men_z135_uart.c | 473 u32 conf_reg; in men_z135_set_mctrl() local
475 conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG); in men_z135_set_mctrl()
477 conf_reg |= MEN_Z135_MCR_RTS; in men_z135_set_mctrl()
479 conf_reg &= ~MEN_Z135_MCR_RTS; in men_z135_set_mctrl()
482 conf_reg |= MEN_Z135_MCR_DTR; in men_z135_set_mctrl()
484 conf_reg &= ~MEN_Z135_MCR_DTR; in men_z135_set_mctrl()
487 conf_reg |= MEN_Z135_MCR_OUT1; in men_z135_set_mctrl()
489 conf_reg &= ~MEN_Z135_MCR_OUT1; in men_z135_set_mctrl()
492 conf_reg |= MEN_Z135_MCR_OUT2; in men_z135_set_mctrl()
494 conf_reg &= ~MEN_Z135_MCR_OUT2; in men_z135_set_mctrl()
[all …]
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| /linux-6.12.1/drivers/pinctrl/freescale/ |
| D | pinctrl-imx.c | 302 if (pin_reg->conf_reg == -1) { in imx_pinconf_get_mmio()
308 *config = readl(ipctl->base + pin_reg->conf_reg); in imx_pinconf_get_mmio()
337 if (pin_reg->conf_reg == -1) { in imx_pinconf_set_mmio()
349 reg = readl(ipctl->base + pin_reg->conf_reg); in imx_pinconf_set_mmio()
352 writel(reg, ipctl->base + pin_reg->conf_reg); in imx_pinconf_set_mmio()
354 pin_reg->conf_reg, reg); in imx_pinconf_set_mmio()
356 writel(configs[i], ipctl->base + pin_reg->conf_reg); in imx_pinconf_set_mmio()
358 pin_reg->conf_reg, configs[i]); in imx_pinconf_set_mmio()
399 if (pin_reg->conf_reg == -1) { in imx_pinconf_dbg_show()
404 config = readl(ipctl->base + pin_reg->conf_reg); in imx_pinconf_dbg_show()
[all …]
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| D | pinctrl-imx.h | 62 * @conf_reg: config register offset
66 s16 conf_reg; member
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| D | pinctrl-imx-scmi.c | 65 int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val; in pinctrl_scmi_imx_dt_node_to_map() local
108 conf_reg = be32_to_cpu(*list++); in pinctrl_scmi_imx_dt_node_to_map()
120 if (!conf_reg || (conf_val & IMX_SCMI_NO_PAD_CTL)) in pinctrl_scmi_imx_dt_node_to_map()
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| /linux-6.12.1/Documentation/devicetree/bindings/firmware/ |
| D | nxp,imx95-scmi-pinctrl.yaml | 29 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
40 "conf_reg" indicates the offset of pad configuration register.
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| /linux-6.12.1/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imxrt1050.yaml | 36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
47 "conf_reg" indicates the offset of pad configuration register.
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| D | fsl,imxrt1170.yaml | 36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
47 "conf_reg" indicates the offset of pad configuration register.
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| D | fsl,imx9-pinctrl.yaml | 40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
51 "conf_reg" indicates the offset of pad configuration register.
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| D | fsl,imx8m-pinctrl.yaml | 39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
51 "conf_reg" indicates the offset of pad configuration register.
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| D | fsl,imx6ul-pinctrl.yaml | 40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
51 "conf_reg" indicates the offset of pad configuration register.
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| D | fsl,imx7d-pinctrl.yaml | 44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
55 "conf_reg" indicates the offset of pad configuration register.
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| D | fsl,imx6sx-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx6sll-pinctrl.txt | 9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| D | fsl,imx-pinctrl.txt | 26 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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| /linux-6.12.1/drivers/hwmon/ |
| D | emc2103.c | 426 u8 conf_reg; in pwm1_enable_store() local
445 result = read_u8_from_i2c(client, REG_FAN_CONF1, &conf_reg); in pwm1_enable_store()
452 conf_reg |= 0x80; in pwm1_enable_store()
454 conf_reg &= ~0x80; in pwm1_enable_store()
456 i2c_smbus_write_byte_data(client, REG_FAN_CONF1, conf_reg); in pwm1_enable_store()
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| /linux-6.12.1/drivers/pinctrl/intel/ |
| D | pinctrl-baytrail.c | 737 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); in byt_gpio_direct_irq_check() local
745 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) in byt_gpio_direct_irq_check()
850 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); in byt_pin_config_get() local
857 conf = readl(conf_reg); in byt_pin_config_get()
933 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); in byt_pin_config_set() local
942 conf = readl(conf_reg); in byt_pin_config_set()
1018 writel(conf, conf_reg); in byt_pin_config_set()
1141 void __iomem *conf_reg, *val_reg; in byt_gpio_dbg_show() local
1148 conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); in byt_gpio_dbg_show()
1149 if (!conf_reg) { in byt_gpio_dbg_show()
[all …]
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| /linux-6.12.1/drivers/watchdog/ |
| D | bd96801_wdt.c | 238 unsigned int conf_reg) in bd96801_set_heartbeat_from_hw() argument
248 if ((conf_reg & BD96801_WD_EN_MASK) != BD96801_WD_IF_EN) { in bd96801_set_heartbeat_from_hw()
263 if ((conf_reg & BD96801_WD_TYPE_MASK) == BD96801_WD_TYPE_WIN) in bd96801_set_heartbeat_from_hw()
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| /linux-6.12.1/drivers/crypto/rockchip/ |
| D | rk3288_crypto_skcipher.c | 258 u32 block, conf_reg = 0; in rk_cipher_hw_init() local
268 conf_reg = RK_CRYPTO_DESSEL; in rk_cipher_hw_init()
281 conf_reg |= RK_CRYPTO_BYTESWAP_BTFIFO | in rk_cipher_hw_init()
283 CRYPTO_WRITE(dev, RK_CRYPTO_CONF, conf_reg); in rk_cipher_hw_init()
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| /linux-6.12.1/arch/arm/boot/dts/nxp/imx/ |
| D | imx6ull-pinfunc-snvs.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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| D | imx6ull-pinfunc.h | 12 * <mux_reg conf_reg input_reg mux_mode input_val>
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| D | imx25-pinfunc.h | 13 * <mux_reg conf_reg input_reg mux_mode input_val>
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| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | imx93-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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| D | imx8mq-pinfunc.h | 12 * <mux_reg conf_reg input_reg mux_mode input_val>
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| D | imx8mm-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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| D | imx8mn-pinfunc.h | 11 * <mux_reg conf_reg input_reg mux_mode input_val>
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