| /linux-6.12.1/Documentation/devicetree/bindings/arm/marvell/ |
| D | coherency-fabric.txt | 1 Coherency fabric
9 * "marvell,coherency-fabric", to be used for the coherency fabric of
12 * "marvell,armada-375-coherency-fabric", for the Armada 375 coherency
15 * "marvell,armada-380-coherency-fabric", for the Armada 38x coherency
18 - reg: Should contain coherency fabric registers location and
21 * For "marvell,coherency-fabric", the first pair for the coherency
24 * For "marvell,armada-375-coherency-fabric", only one pair is needed
27 * For "marvell,armada-380-coherency-fabric", only one pair is needed
37 coherency-fabric@d0020200 {
38 compatible = "marvell,coherency-fabric";
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| /linux-6.12.1/arch/arm/mach-mvebu/ |
| D | coherency.c | 3 * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
12 * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
13 * responsible for ensuring hardware coherency between all CPUs and between
14 * CPUs and I/O masters. This file initializes the coherency fabric and
15 * supplies basic routines for configuring and controlling hardware coherency
18 #define pr_fmt(fmt) "mvebu-coherency: " fmt
34 #include "coherency.h"
42 /* Coherency fabric registers */
53 {.compatible = "marvell,coherency-fabric",
55 {.compatible = "marvell,armada-375-coherency-fabric",
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| D | coherency_ll.S | 3 * Coherency fabric: low level functions
10 * coherency fabric. This function is called by each of the secondary
26 * Returns the coherency base address in r1 (r0 is untouched), or 0 if
27 * the coherency fabric is not enabled.
35 * MMU is disabled, use the physical address of the coherency
36 * base address, (or 0x0 if the coherency fabric is not mapped)
44 * MMU is enabled, use the virtual address of the coherency
54 * Returns the coherency CPU mask in r3 (r0 is untouched). This
55 * coherency CPU mask can be used with the coherency fabric
58 * have to care about endianness issues while accessing the coherency
[all …]
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| D | coherency.h | 3 * arch/arm/mach-mvebu/include/mach/coherency.h
5 * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
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| D | headsmp.S | 13 * the coherency fabric by writing to 2 registers. Currently the base
25 * We add the CPU to the coherency fabric and then jump to secondary
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| /linux-6.12.1/Documentation/filesystems/caching/ |
| D | netfs-api.rst | 18 (4) Cookies have coherency data that allows a cache to determine if the
35 (7) Data file coherency
72 for the cookie in the background, to check its coherency and, if necessary, to
104 and notes the coherency data.
116 The specified coherency data is stored in the cookie and will be matched
117 against coherency data stored on disk. The data pointer may be NULL if no data
118 is provided. If the coherency data doesn't match, the entire cache volume will
136 coherency data will be set to the value supplied. The amount of coherency data
163 The caller should also pass in a piece of coherency data in aux_data. A buffer
164 of size aux_data_len will be allocated and the coherency data copied in. It is
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| D | backend-api.rst | 147 u8 coherency[];
165 * ``coherency`` - A piece of coherency data that should be checked when the
168 * ``coherency_len`` - The amount of data in the coherency buffer.
203 * FSCACHE_COOKIE_NEEDS_UPDATE - The coherency data and/or object size has
227 * ``aux_len`` - The length of the coherency data buffer.
237 Each cookie also has a buffer for coherency data. This may also be inline or
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| /linux-6.12.1/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/ |
| D | cache.json | 189 …e write-back. This event occurs when a requestor outside the PE makes a coherency request that res…
192 …e write-back. This event occurs when a requestor outside the PE makes a coherency request that res…
195 …cache access. This event occurs when a requestor outside the PE makes a coherency request that res…
198 …cache access. This event occurs when a requestor outside the PE makes a coherency request that res…
201 …access, read. This event occurs when a requestor outside the PE makes a coherency request that res…
204 …access, read. This event occurs when a requestor outside the PE makes a coherency request that res…
207 …cache access. This event occurs when a requestor outside the PE makes a coherency request that res…
210 …cache access. This event occurs when a requestor outside the PE makes a coherency request that res…
213 …access, read. This event occurs when a requestor outside the PE makes a coherency request that res…
216 …access, read. This event occurs when a requestor outside the PE makes a coherency request that res…
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| /linux-6.12.1/Documentation/arch/arm/ |
| D | cluster-pm-race-avoidance.rst | 6 cluster setup and teardown operations and to manage hardware coherency
33 mechanisms like Linux spinlocks may rely on coherency mechanisms which
73 enabling coherency.
83 coherency exit.
160 A CPU cannot start participating in hardware coherency until the
178 start participating in local coherency.
201 While in this state, the CPU exits coherency, including any
318 enabling of hardware coherency at the cluster level and any
323 setup to enable other CPUs in the cluster to enter coherency
329 cluster-level setup and hardware coherency complete
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | ccf.txt | 1 Freescale CoreNet Coherency Fabric(CCF) Device Tree Binding
5 The CoreNet coherency fabric is a fabric-oriented, connectivity infrastructure
11 fsl,corenet1-cf - CoreNet coherency fabric version 1.
14 fsl,corenet2-cf - CoreNet coherency fabric version 2.
31 Specifies the number of Coherency Subdomain ID Port Mapping
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| D | cpus.txt | 27 Definition: The Coherency Subdomain ID Port Mapping Registers and
29 Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
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| D | pamu.txt | 36 The Coherency Subdomain ID Port Mapping Registers and
38 CoreNet Coherency fabric (CCF), provide a CoreNet
39 Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
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| /linux-6.12.1/arch/mips/mti-malta/ |
| D | malta-setup.c | 100 pr_info("Enabled Bonito CPU coherency\n"); in plat_setup_iocoherency()
108 pr_info("Disabled Bonito IOBC coherency\n"); in plat_setup_iocoherency()
114 pr_info("Enabled Bonito IOBC coherency\n"); in plat_setup_iocoherency()
117 /* Nothing special needs to be done to enable coherency */ in plat_setup_iocoherency()
123 pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); in plat_setup_iocoherency()
127 pr_info("Hardware DMA cache coherency enabled\n"); in plat_setup_iocoherency()
129 pr_info("Software DMA cache coherency enabled\n"); in plat_setup_iocoherency()
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| /linux-6.12.1/arch/arm64/include/asm/ |
| D | cacheflush.h | 39 * Ensure coherency between the I-cache and the D-cache region to
44 * Ensure coherency between the I-cache and the D-cache region to
54 * Clean and invalidate D-cache region to the Point of Coherency.
58 * Invalidate D-cache region to the Point of Coherency.
62 * Clean D-cache region to the Point of Coherency.
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| /linux-6.12.1/drivers/gpu/drm/xe/ |
| D | xe_pat.h | 22 * caching, coherency, compression etc can be encoded here.
27 * @coh_mode: The GPU coherency mode that @value maps to.
54 * xe_pat_index_get_coh_mode - Extract the coherency mode for the given
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/jaketown/ |
| D | uncore-io.json | 17 … NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common)…
27 … NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common)…
37 … NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common)…
47 … NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common)…
57 … NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common)…
67 … NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common)…
77 … NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common)…
87 … NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common)…
97 … NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common)…
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| /linux-6.12.1/include/drm/ |
| D | drm_cache.h | 64 * platform where NoSnoop is ignored results in loss of coherency, which in drm_arch_can_wc_memory()
72 * LoongArch maintains cache coherency in hardware, but its WUC attribute in drm_arch_can_wc_memory()
74 * cache coherency machanism. This means WUC can only used for write-only in drm_arch_can_wc_memory()
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| /linux-6.12.1/drivers/memory/ |
| D | fsl-corenet-cf.c | 3 * CoreNet Coherency Fabric error reporting
74 #define ERRDET_CV (1 << 1) /* Coherency Violation */
152 dev_crit(ccf->dev, "Coherency Violation\n"); in ccf_irq()
259 MODULE_DESCRIPTION("Freescale CoreNet Coherency Fabric error reporting");
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/broadwellde/ |
| D | uncore-interconnect.json | 36 "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
46 "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
56 "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
66 "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
76 "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
86 "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
96 "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
106 "PublicDescription": "Counts the number of coherency related operations servied by the IRP",
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| /linux-6.12.1/Documentation/filesystems/ |
| D | ocfs2.rst | 106 coherency=full (*) Disallow concurrent O_DIRECT writes, cluster inode
108 therefore full cluster coherency is guaranteed even
110 coherency=buffered Allow concurrent O_DIRECT writes without EX lock among
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/haswell/ |
| D | uncore-interconnect.json | 3 …"BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allo…
8 …"PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from all…
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| /linux-6.12.1/fs/cachefiles/ |
| D | xattr.c | 25 __u8 data[]; /* netfs coherency data */
33 __u8 data[]; /* netfs volume coherency data */
209 const void *p = volume->vcookie->coherency; in cachefiles_set_volume_xattr()
258 const void *p = volume->vcookie->coherency; in cachefiles_check_volume_xattr()
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| /linux-6.12.1/arch/arm/mach-shmobile/ |
| D | platsmp-scu.c | 35 /* enable SCU and cache coherency on booting CPU */ in shmobile_smp_scu_prepare_cpus()
56 /* disable cache coherency */ in shmobile_smp_scu_cpu_die()
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| /linux-6.12.1/include/linux/ |
| D | fscache.h | 91 u8 coherency_len; /* Length of the coherency data */
92 u8 coherency[]; /* Coherency data */ member
187 * @coherency_data: Piece of arbitrary coherency data to check (or NULL)
188 * @coherency_len: The size of the coherency data
193 * the coherency data must match otherwise the entry will be invalidated.
214 * @coherency_data: Piece of arbitrary coherency data to set (or NULL)
219 * The stored coherency data is updated.
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/sandybridge/ |
| D | uncore-interconnect.json | 3 "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.",
12 "BriefDescription": "Number of requests allocated in Coherency Tracker.",
|