Searched full:clock (Results 1 – 25 of 7643) sorted by relevance
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
D | am43xx-clocks.dtsi | 3 * Device Tree Source for AM43xx clock data 8 sys_clkin_ck: clock-sys-clkin-31@40 { 9 #clock-cells = <0>; 10 compatible = "ti,mux-clock"; 11 clock-output-names = "sys_clkin_ck"; 17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 { 18 #clock-cells = <0>; 19 compatible = "ti,mux-clock"; 20 clock-output-names = "crystal_freq_sel_ck"; 26 sysboot_freq_sel_ck: clock-sysboot-freq-sel-22@44e10040 { [all …]
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D | am33xx-clocks.dtsi | 3 * Device Tree Source for AM33xx clock data 8 sys_clkin_ck: clock-sys-clkin-22@40 { 9 #clock-cells = <0>; 10 compatible = "ti,mux-clock"; 11 clock-output-names = "sys_clkin_ck"; 17 adc_tsc_fck: clock-adc-tsc-fck { 18 #clock-cells = <0>; 19 compatible = "fixed-factor-clock"; 20 clock-output-names = "adc_tsc_fck"; 22 clock-mult = <1>; [all …]
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D | omap3xxx-clocks.dtsi | 3 * Device Tree Source for OMAP3 clock data 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-frequency = <16800000>; 15 #clock-cells = <0>; 16 compatible = "ti,mux-clock"; 22 #clock-cells = <0>; 23 compatible = "ti,divider-clock"; 32 #clock-cells = <0>; 33 compatible = "ti,gate-clock"; [all …]
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D | dra7xx-clocks.dtsi | 3 * Device Tree Source for DRA7xx clock data 8 atl_clkin0_ck: clock-atl-clkin0 { 9 #clock-cells = <0>; 10 compatible = "ti,dra7-atl-clock"; 11 clock-output-names = "atl_clkin0_ck"; 15 atl_clkin1_ck: clock-atl-clkin1 { 16 #clock-cells = <0>; 17 compatible = "ti,dra7-atl-clock"; 18 clock-output-names = "atl_clkin1_ck"; 22 atl_clkin2_ck: clock-atl-clkin2 { [all …]
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D | omap54xx-clocks.dtsi | 3 * Device Tree Source for OMAP5 clock data 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "pad_clks_src_ck"; 12 clock-frequency = <12000000>; 16 #clock-cells = <0>; 17 compatible = "ti,gate-clock"; 18 clock-output-names = "pad_clks_ck"; 25 #clock-cells = <0>; 26 compatible = "fixed-clock"; [all …]
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D | omap44xx-clocks.dtsi | 3 * Device Tree Source for OMAP4 clock data 9 #clock-cells = <0>; 10 compatible = "fixed-clock"; 11 clock-output-names = "extalt_clkin_ck"; 12 clock-frequency = <59000000>; 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 clock-output-names = "pad_clks_src_ck"; 19 clock-frequency = <12000000>; 23 #clock-cells = <0>; [all …]
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D | omap24xx-clocks.dtsi | 3 * Device Tree Source for OMAP24xx clock data 9 #clock-cells = <0>; 10 compatible = "ti,composite-mux-clock"; 17 #clock-cells = <0>; 18 compatible = "ti,composite-clock"; 23 #clock-cells = <0>; 24 compatible = "ti,composite-mux-clock"; 31 #clock-cells = <0>; 32 compatible = "ti,composite-clock"; 39 #clock-cells = <0>; [all …]
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D | dm814x-clocks.dtsi | 10 #clock-cells = <1>; 11 compatible = "ti,dm814-adpll-s-clock"; 14 clock-names = "clkinp", "clkinpulow", "clkinphif"; 15 clock-output-names = "481c5040.adpll.dcoclkldo", 22 #clock-cells = <1>; 23 compatible = "ti,dm814-adpll-lj-clock"; 26 clock-names = "clkinp", "clkinpulow"; 27 clock-output-names = "481c5080.adpll.dcoclkldo", 33 #clock-cells = <1>; 34 compatible = "ti,dm814-adpll-lj-clock"; [all …]
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D | omap36xx-omap3430es2plus-clocks.dtsi | 3 * Device Tree Source for OMAP34xx/OMAP36xx clock data 8 clock@a00 { 11 #clock-cells = <2>; 15 ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2@0 { 17 #clock-cells = <0>; 18 compatible = "ti,composite-no-wait-gate-clock"; 19 clock-output-names = "ssi_ssr_gate_fck_3430es2"; 24 clock@a40 { 27 #clock-cells = <2>; 31 ssi_ssr_div_fck_3430es2: clock-ssi-ssr-div-fck-3430es2@8 { [all …]
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D | omap34xx-omap36xx-clocks.dtsi | 3 * Device Tree Source for OMAP34XX/OMAP36XX clock data 9 #clock-cells = <0>; 10 compatible = "fixed-factor-clock"; 12 clock-mult = <1>; 13 clock-div = <1>; 16 clock@a14 { 19 #clock-cells = <2>; 23 aes1_ick: clock-aes1-ick@3 { 25 #clock-cells = <0>; 26 compatible = "ti,omap3-interface-clock"; [all …]
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/linux-6.12.1/arch/mips/boot/dts/mobileye/ |
D | eyeq5-clocks.dtsi | 6 #include <dt-bindings/clock/mobileye,eyeq5-clk.h> 9 /* Fixed clock */ 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <30000000>; 18 compatible = "fixed-factor-clock"; 20 #clock-cells = <0>; 21 clock-div = <1>; 22 clock-mult = <1>; 25 compatible = "fixed-factor-clock"; [all …]
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/linux-6.12.1/arch/arm/boot/dts/ti/keystone/ |
D | keystone-clocks.dtsi | 3 * Device Tree Source for Keystone 2 clock tree 14 #clock-cells = <0>; 15 compatible = "ti,keystone,pll-mux-clock"; 20 clock-output-names = "mainmuxclk"; 24 #clock-cells = <0>; 25 compatible = "fixed-factor-clock"; 27 clock-div = <1>; 28 clock-mult = <1>; 29 clock-output-names = "chipclk1"; 33 #clock-cells = <0>; [all …]
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D | keystone-k2hk-clocks.dtsi | 3 * Keystone 2 Kepler/Hawking SoC clock nodes 10 #clock-cells = <0>; 11 compatible = "ti,keystone,pll-clock"; 13 clock-output-names = "arm-pll-clk"; 19 #clock-cells = <0>; 20 compatible = "ti,keystone,main-pll-clock"; 27 #clock-cells = <0>; 28 compatible = "ti,keystone,pll-clock"; 30 clock-output-names = "papllclk"; 36 #clock-cells = <0>; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/clock/ |
D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU) 4 peripheral blocks of the LPC18xx. Each independent clock is called 5 a base clock and itself is one of the inputs to the two Clock 9 The CGU selects the inputs to the clock generators from multiple 10 clock sources, controls the clock generation, and routes the outputs 11 of the clock generators through the clock source bus to the output 12 stages. Each output stage provides an independent clock source and 18 This binding uses the common clock binding: 19 Documentation/devicetree/bindings/clock/clock-bindings.txt 26 containing clock control registers [all …]
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D | mvebu-core-clock.txt | 1 * Core Clock bindings for Marvell MVEBU SoCs 3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by 4 reading the Sample-At-Reset (SAR) register. The core clock consumer should 5 specify the desired clock by having the clock ID in its "clocks" phandle cell. 7 The following is a list of provided IDs and clock names on Armada 370/XP: 8 0 = tclk (Internal Bus clock) 9 1 = cpuclk (CPU clock) 10 2 = nbclk (L2 Cache clock) 11 3 = hclk (DRAM control clock) 12 4 = dramclk (DDR clock) [all …]
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D | qcom,mmcc.yaml | 4 $id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml# 7 title: Qualcomm Multimedia Clock & Reset Controller 14 Qualcomm multimedia clock control module provides the clocks, resets and 37 clock-names: 41 '#clock-cells': 55 Protected clock specifier list as per common clock binding 64 - '#clock-cells' 83 - description: PLL 3 clock 84 - description: PLL 3 Vote clock 85 - description: DSI phy instance 1 dsi clock [all …]
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D | samsung,exynos5260-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml# 7 title: Samsung Exynos5260 SoC clock controller 18 - "fin_pll" - PLL input clock from XXTI 19 - "xrtcxti" - input clock from XRTCXTI 20 - "ioclk_pcm_extclk" - pcm external operation clock 21 - "ioclk_spdif_extclk" - spdif external operation clock 22 - "ioclk_i2s_cdclk" - i2s0 codec clock 26 are fed into the clock controller and then routed to the hardware blocks. 28 - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 29 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 [all …]
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D | st,stm32mp25-rcc.yaml | 4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml# 7 title: STM32MP25 Reset Clock Controller 13 The RCC hardware block is both a reset and a clock controller. 17 include/dt-bindings/clock/st,stm32mp25-rcc.h 28 '#clock-cells': 42 - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock 43 - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock 44 - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock 45 - description: CK_SCMI_ICN_DDR DDR interconnect bus clock 46 - description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock [all …]
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D | tesla,fsd-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml# 7 title: Tesla FSD (Full Self-Driving) SoC clock controller 14 FSD clock controller consist of several clock management unit 16 The root clock comes from external OSC clock (24 MHz). 19 'dt-bindings/clock/fsd-clk.h' header. 24 - tesla,fsd-clock-cmu 25 - tesla,fsd-clock-imem 26 - tesla,fsd-clock-peric 27 - tesla,fsd-clock-fsys0 28 - tesla,fsd-clock-fsys1 [all …]
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/linux-6.12.1/drivers/clk/qcom/ |
D | Kconfig | 11 tristate "Support for Qualcomm's clock controllers" 23 tristate "X1E80100 Camera Clock Controller" 27 Support for the camera clock controller on X1E80100 devices. 31 tristate "X1E80100 Display Clock Controller" 35 Support for the two display clock controllers on Qualcomm 41 tristate "X1E80100 Global Clock Controller" 45 Support for the global clock controller on Qualcomm Technologies, Inc 51 tristate "X1E80100 Graphics Clock Controller" 55 Support for the graphics clock controller on X1E80100 devices. 60 tristate "X1E80100 TCSR Clock Controller" [all …]
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/linux-6.12.1/arch/arm/boot/dts/st/ |
D | ste-nomadik-stn8815.dtsi | 41 clock-names = "timclk", "apb_pclk"; 50 clock-names = "timclk", "apb_pclk"; 199 #clock-cells = <0>; 200 compatible = "fixed-clock"; 201 clock-frequency = <19200000>; 205 * The 2.4 MHz TIMCLK reference clock is active at 207 * divided by 8. This clock is used by the timers and 211 #clock-cells = <0>; 212 compatible = "fixed-factor-clock"; 213 clock-div = <8>; [all …]
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/linux-6.12.1/arch/arm/boot/dts/samsung/ |
D | exynos5420.dtsi | 14 #include <dt-bindings/clock/exynos5420.h> 15 #include <dt-bindings/clock/exynos-audss-clk.h> 39 clocks = <&clock CLK_DOUT_ACLK400_DISP1>; 40 clock-names = "bus"; 46 clocks = <&clock CLK_DOUT_ACLK300_DISP1>; 47 clock-names = "bus"; 53 clocks = <&clock CLK_DOUT_ACLK200_FSYS>; 54 clock-names = "bus"; 60 clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; 61 clock-names = "bus"; [all …]
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D | exynos5410.dtsi | 14 #include <dt-bindings/clock/exynos5410.h> 15 #include <dt-bindings/clock/exynos-audss-clk.h> 37 clock-frequency = <1600000000>; 44 clock-frequency = <1600000000>; 51 clock-frequency = <1600000000>; 58 clock-frequency = <1600000000>; 71 clock-names = "clkout16"; 73 #clock-cells = <1>; 76 clock: clock-controller@10010000 { label 77 compatible = "samsung,exynos5410-clock"; [all …]
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/linux-6.12.1/drivers/clk/mediatek/ |
D | Kconfig | 3 # MediaTek Clock Drivers 5 menu "Clock driver for MediaTek SoC" 12 MediaTek SoCs' clock support. 15 bool "clock driver for MediaTek FHCTL hardware control" 22 bool "Clock driver for MediaTek MT2701" 30 bool "Clock driver for MediaTek MT2701 mmsys" 36 bool "Clock driver for MediaTek MT2701 imgsys" 42 bool "Clock driver for MediaTek MT2701 vdecsys" 48 bool "Clock driver for MediaTek MT2701 hifsys" 54 bool "Clock driver for MediaTek MT2701 ethsys" [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/clock/ti/ |
D | gate.txt | 1 Binding for Texas Instruments gate clock. 3 This binding uses the common clock binding[1]. This clock is 4 quite much similar to the basic gate-clock [2], however, 6 is provided for this clock, the code assumes that a clockdomain 10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 11 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml 12 [3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt 16 "ti,gate-clock" - basic gate clock 17 "ti,wait-gate-clock" - gate clock which waits until clock is active before 19 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling [all …]
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