Searched +full:clock +full:- +full:controller (Results 1 – 25 of 1181) sorted by relevance
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/linux-6.12.1/drivers/clk/qcom/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 11 tristate "Support for Qualcomm's clock controllers" 23 tristate "X1E80100 Camera Clock Controller" 27 Support for the camera clock controller on X1E80100 devices. 31 tristate "X1E80100 Display Clock Controller" 35 Support for the two display clock controllers on Qualcomm 41 tristate "X1E80100 Global Clock Controller" 45 Support for the global clock controller on Qualcomm Technologies, Inc 51 tristate "X1E80100 Graphics Clock Controller" 55 Support for the graphics clock controller on X1E80100 devices. [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/clock/ |
D | mediatek,mt8195-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek Functional Clock Controller for MT8195 10 - Chun-Jie Chen <chun-jie.chen@mediatek.com> 13 The clock architecture in Mediatek like below 14 PLLs --> 15 dividers --> 17 --> [all …]
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D | mediatek,mt8192-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: MediaTek Functional Clock Controller for MT8192 10 - Chun-Jie Chen <chun-jie.chen@mediatek.com> 13 The Mediatek functional clock controller provides various clocks on MT8192. 18 - enum: 19 - mediatek,mt8192-scp_adsp 20 - mediatek,mt8192-imp_iic_wrap_c [all …]
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D | pistachio-clock.txt | 1 Imagination Technologies Pistachio SoC clock controllers 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral 6 from the device-tree. 9 ---------------- 11 There are three external inputs to the clock controllers which should be 12 defined with the following clock-output-names: 13 - "xtal": External 52Mhz oscillator (required) 14 - "audio_clk_in": Alternate audio reference clock (optional) 15 - "enet_clk_in": Alternate ethernet PHY clock (optional) 17 Core clock controller: [all …]
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D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller 3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which 10 clk_sysbypck are inputs to the clock controller. 12 network. They are set on the device tree, but not used by the clock module. The 17 dt-bindings/clock/nuvoton,npcm7xx-clock.h 20 Required Properties of clock controller: 22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton 25 - reg: physical base address of the clock controller and length of 28 - #clock-cells: should be 1. 30 Example: Clock controller node: [all …]
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/linux-6.12.1/drivers/clk/rockchip/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 2 # common clock support for ROCKCHIP SoC family. 5 bool "Rockchip clock controller common support" 9 Say y here to enable common clock controller for Rockchip platforms. 13 bool "Rockchip PX30 clock controller support" 17 Build the driver for PX30 Clock Driver. 20 bool "Rockchip RV110x clock controller support" 24 Build the driver for RV110x Clock Driver. 27 bool "Rockchip RV1126 clock controller support" 31 Build the driver for RV1126 Clock Driver. [all …]
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/linux-6.12.1/drivers/clk/samsung/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 4 bool "Samsung Exynos clock controller support" if COMPILE_TEST 18 bool "Samsung S3C64xx clock controller support" if COMPILE_TEST 21 Support for the clock controller present on the Samsung S3C64xx SoCs. 25 bool "Samsung S5Pv210 clock controller support" if COMPILE_TEST 28 Support for the clock controller present on the Samsung S5Pv210 SoCs. 32 bool "Samsung Exynos3250 clock controller support" if COMPILE_TEST 35 Support for the clock controller present on the Samsung 39 bool "Samsung Exynos4 clock controller support" if COMPILE_TEST 42 Support for the clock controller present on the Samsung [all …]
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/linux-6.12.1/drivers/clk/meson/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 2 menu "Clock support for Amlogic platforms" 56 bool "Meson8 SoC Clock controller support" 66 Support for the clock controller on AmLogic S802 (Meson8), 71 tristate "GXBB and GXL SoC clock controllers support" 83 Support for the clock controller on AmLogic S905 devices, aka gxbb. 87 tristate "AXG SoC clock controllers support" 98 Support for the clock controller on AmLogic A113D devices, aka axg. 102 tristate "Meson AXG Audio Clock Controller Driver" 110 Support for the audio clock controller on AmLogic A113D devices, [all …]
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/linux-6.12.1/arch/arm/boot/dts/hisilicon/ |
D | hisi-x5hd2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2013-2014 Linaro Ltd. 4 * Copyright (c) 2013-2014 HiSilicon Limited. 7 #include <dt-bindings/clock/hix5hd2-clock.h> 10 #address-cells = <1>; 11 #size-cells = <1>; 17 gic: interrupt-controller@f8a01000 { 18 compatible = "arm,cortex-a9-gic"; 19 #interrupt-cells = <3>; 20 #address-cells = <0>; [all …]
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D | hi3620.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012-2013 HiSilicon Ltd. 6 * Copyright (C) 2012-2013 Linaro Ltd. 11 #include <dt-bindings/clock/hi3620-clock.h> 14 #address-cells = <1>; 15 #size-cells = <1>; 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <26000000>; 29 clock-output-names = "apb_pclk"; [all …]
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/linux-6.12.1/include/soc/canaan/ |
D | k210-sysctl.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 10 * Kendryte K210 SoC system controller registers offsets. 11 * Taken from Kendryte SDK (kendryte-standalone-sdk). 15 #define K210_SYSCTL_PLL0 0x08 /* PLL0 controller */ 16 #define K210_SYSCTL_PLL1 0x0C /* PLL1 controller */ 17 #define K210_SYSCTL_PLL2 0x10 /* PLL2 controller */ 20 #define K210_SYSCTL_SEL0 0x20 /* Clock select controller 0 */ 21 #define K210_SYSCTL_SEL1 0x24 /* Clock select controller 1 */ 22 #define K210_SYSCTL_EN_CENT 0x28 /* Central clock enable */ [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | imx8-ss-lsio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2020 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 10 lsio_bus_clk: clock-lsio-bus { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <100000000>; 14 clock-output-names = "lsio_bus_clk"; 18 compatible = "simple-bus"; [all …]
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D | imx8-ss-mipi0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only and MIT 8 compatible = "simple-bus"; 9 interrupt-parent = <&irqsteer_mipi0>; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 irqsteer_mipi0: interrupt-controller@56220000 { 15 compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer"; 18 interrupt-controller; 19 interrupt-parent = <&gic>; 20 #interrupt-cells = <1>; [all …]
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D | imx8-ss-mipi1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only and MIT 8 compatible = "simple-bus"; 9 interrupt-parent = <&irqsteer_mipi1>; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 irqsteer_mipi1: interrupt-controller@57220000 { 15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 18 interrupt-controller; 19 interrupt-parent = <&gic>; 20 #interrupt-cells = <1>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/hisilicon/ |
D | hi3670.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/clock/hi3670-clock.h> 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 19 compatible = "arm,psci-0.2"; 24 #address-cells = <2>; 25 #size-cells = <0>; 27 cpu-map { [all …]
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/linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
D | mt6779.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 8 #include <dt-bindings/clock/mt6779-clk.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/pinctrl/mt6779-pinfunc.h> 15 interrupt-parent = <&sysirq>; 16 #address-cells = <2>; 17 #size-cells = <2>; 20 compatible = "arm,psci-0.2"; 25 #address-cells = <1>; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/arm/hisilicon/controller/ |
D | sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Hisilicon system controller 10 - Wei Xu <xuwei5@hisilicon.com> 13 The Hisilicon system controller is used on many Hisilicon boards, it can be 16 There are some variants of the Hisilicon system controller, such as HiP01, 17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the 18 Hisilicon system controller, but some same registers located at different [all …]
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/linux-6.12.1/arch/arm64/boot/dts/lg/ |
D | lg1313.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #address-cells = <2>; 13 #size-cells = <2>; 16 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <0>; 24 compatible = "arm,cortex-a53"; 26 next-level-cache = <&L2_0>; [all …]
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D | lg1312.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #address-cells = <2>; 13 #size-cells = <2>; 16 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <0>; 24 compatible = "arm,cortex-a53"; 26 next-level-cache = <&L2_0>; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/soc/amlogic/ |
D | amlogic,meson-gx-hhi-sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Neil Armstrong <neil.armstrong@linaro.org> 15 - enum: 16 - amlogic,meson-gx-hhi-sysctrl 17 - amlogic,meson-gx-ao-sysctrl 18 - amlogic,meson-axg-hhi-sysctrl 19 - amlogic,meson-axg-ao-sysctrl [all …]
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/linux-6.12.1/Documentation/gpu/amdgpu/display/ |
D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere, 19 Application-Specific Integrated Circuit 34 * PCLK: Pixel Clock 35 * SYMCLK: Symbol Clock 36 * SOCCLK: GPU Engine Clock 37 * DISPCLK: Display Clock 38 * DPPCLK: DPP Clock 39 * DCFCLK: Display Controller Fabric Clock 40 * REFCLK: Real Time Reference Clock 42 * FCLK: Fabric Clock [all …]
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/linux-6.12.1/arch/mips/boot/dts/ingenic/ |
D | jz4740.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 3 #include <dt-bindings/clock/ingenic,tcu.h> 6 #address-cells = <1>; 7 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 16 compatible = "ingenic,xburst-mxu1.0"; 20 clock-names = "cpu"; 24 cpuintc: interrupt-controller { [all …]
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D | jz4770.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 3 #include <dt-bindings/clock/ingenic,tcu.h> 6 #address-cells = <1>; 7 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 16 compatible = "ingenic,xburst-fpu1.0-mxu1.1"; 20 clock-names = "cpu"; 24 cpuintc: interrupt-controller { [all …]
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D | jz4725b.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h> 3 #include <dt-bindings/clock/ingenic,tcu.h> 6 #address-cells = <1>; 7 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 16 compatible = "ingenic,xburst-mxu1.0"; 20 clock-names = "cpu"; 24 cpuintc: interrupt-controller { [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/mfd/ |
D | canaan,k210-sysctl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Canaan Kendryte K210 System Controller 10 - Damien Le Moal <dlemoal@kernel.org> 13 Canaan Inc. Kendryte K210 SoC system controller which provides a 20 - const: canaan,k210-sysctl 21 - const: syscon 22 - const: simple-mfd [all …]
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