Searched full:clk_csr_i (Results 1 – 7 of 7) sorted by relevance
58 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */59 #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */60 #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */61 #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */62 #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */63 #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */64 #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */65 #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
87 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in loongson_default_data()
420 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
311 * the frequency of clk_csr_i. So we do not change the default in stmmac_clk_csr_set()
81 source connected to the clk_csr_i line.
44 APB, AHB, AXI, etc. The HW signal name is hclk_i (AHB) or clk_csr_i (other