Searched full:clk48m (Results 1 – 5 of 5) sorted by relevance
| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-s3c64xx.c | 100 PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" };
101 PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" };
106 PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" };
107 PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" };
120 FRATE(CLK48M, "clk48m", NULL, 0, 48000000),
247 GATE_SCLK(SCLK_MMC2_48, "sclk_mmc2_48", "clk48m", SCLK_GATE, 29),
248 GATE_SCLK(SCLK_MMC1_48, "sclk_mmc1_48", "clk48m", SCLK_GATE, 28),
249 GATE_SCLK(SCLK_MMC0_48, "sclk_mmc0_48", "clk48m", SCLK_GATE, 27),
253 GATE_SCLK(SCLK_SPI1_48, "sclk_spi1_48", "clk48m", SCLK_GATE, 23),
254 GATE_SCLK(SCLK_SPI0_48, "sclk_spi0_48", "clk48m", SCLK_GATE, 22),
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-imx1.c | 22 static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
53 clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3); in mx1_clocks_init_dt()
64 clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); in mx1_clocks_init_dt()
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | samsung,s3c64xx-clock.h | 21 #define CLK48M 2 macro
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | mediatek,xsphy.yaml | 184 clocks = <&clk48m>;
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| D | mediatek,tphy.yaml | 304 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
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