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/linux-6.12.1/drivers/net/ethernet/sfc/
Defx_channels.c156 * We need a channel per event queue, plus a VI per tx queue. in efx_allocate_msix_channels()
273 /* Fall back to single channel MSI */ in efx_probe_interrupts()
366 struct efx_channel *channel; in efx_set_interrupt_affinity() local
374 efx_for_each_channel(channel, efx) { in efx_set_interrupt_affinity()
378 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); in efx_set_interrupt_affinity()
384 struct efx_channel *channel; in efx_clear_interrupt_affinity() local
386 efx_for_each_channel(channel, efx) in efx_clear_interrupt_affinity()
387 irq_set_affinity_hint(channel->irq, NULL); in efx_clear_interrupt_affinity()
403 struct efx_channel *channel; in efx_remove_interrupts() local
406 efx_for_each_channel(channel, efx) in efx_remove_interrupts()
[all …]
/linux-6.12.1/drivers/net/ethernet/sfc/siena/
Defx_channels.c157 * We need a channel per event queue, plus a VI per tx queue. in efx_allocate_msix_channels()
274 /* Fall back to single channel MSI */ in efx_siena_probe_interrupts()
367 struct efx_channel *channel; in efx_siena_set_interrupt_affinity() local
375 efx_for_each_channel(channel, efx) { in efx_siena_set_interrupt_affinity()
379 irq_set_affinity_hint(channel->irq, cpumask_of(cpu)); in efx_siena_set_interrupt_affinity()
385 struct efx_channel *channel; in efx_siena_clear_interrupt_affinity() local
387 efx_for_each_channel(channel, efx) in efx_siena_clear_interrupt_affinity()
388 irq_set_affinity_hint(channel->irq, NULL); in efx_siena_clear_interrupt_affinity()
404 struct efx_channel *channel; in efx_siena_remove_interrupts() local
407 efx_for_each_channel(channel, efx) in efx_siena_remove_interrupts()
[all …]
/linux-6.12.1/drivers/rpmsg/
Dqcom_smd.c30 * Each channel consists of a control item (channel info) and a ring buffer
31 * pair. The channel info carry information related to channel state, flow
37 * Upon creating a new channel the remote processor allocates channel info and
39 * interrupt is sent to the other end of the channel and a scan for new
40 * channels should be done. A channel never goes away, it will only change
44 * channel by setting the state of its end of the channel to "opening" and
46 * consume the channel. Upon finding a consumer we finish the handshake and the
47 * channel is up.
49 * Upon closing a channel, the remote processor will update the state of its
50 * end of the channel and signal us, we will then unregister any attached
[all …]
Dqcom_glink_native.c71 * @in_use: To mark if intent is already in use for the channel
97 * @lcids: idr of all channels with a known local channel id
98 * @rcids: idr of all channels with a known remote channel id
139 * struct glink_channel - internal representation of a channel
141 * @ept: rpmsg endpoint this channel is associated with
143 * @refcount: refcount for the channel object
145 * @name: unique channel name/identifier
146 * @lcid: channel id, in local space
147 * @rcid: channel id, in remote space
228 struct glink_channel *channel; in qcom_glink_alloc_channel() local
[all …]
Dqcom_glink_trace.h64 TP_PROTO(const char *remote, const char *channel, u16 lcid, u16 rcid, bool tx),
65 TP_ARGS(remote, channel, lcid, rcid, tx),
68 __string(channel, channel)
75 __assign_str(channel);
80 TP_printk("%s remote: %s channel: %s[%u/%u]",
83 __get_str(channel),
92 TP_PROTO(const char *remote, const char *channel, u16 lcid, u16 rcid, bool tx),
93 TP_ARGS(remote, channel, lcid, rcid, tx),
96 __string(channel, channel)
103 __assign_str(channel);
[all …]
/linux-6.12.1/drivers/char/xillybus/
Dxillybus_core.c102 "Malformed message (skipping): opcode=%d, channel=%03x, dir=%d, bufno=%03x, data=%07x\n", in malformed_message()
120 struct xilly_channel *channel; in xillybus_isr() local
177 channel = ep->channels[msg_channel]; in xillybus_isr()
179 if (msg_dir) { /* Write channel */ in xillybus_isr()
180 if (msg_bufno >= channel->num_wr_buffers) { in xillybus_isr()
184 spin_lock(&channel->wr_spinlock); in xillybus_isr()
185 channel->wr_buffers[msg_bufno]->end_offset = in xillybus_isr()
187 channel->wr_fpga_buf_idx = msg_bufno; in xillybus_isr()
188 channel->wr_empty = 0; in xillybus_isr()
189 channel->wr_sleepy = 0; in xillybus_isr()
[all …]
/linux-6.12.1/drivers/staging/greybus/
Dlight.c65 static void gb_lights_channel_free(struct gb_channel *channel);
67 static struct gb_connection *get_conn_from_channel(struct gb_channel *channel) in get_conn_from_channel() argument
69 return channel->light->glights->connection; in get_conn_from_channel()
77 static bool is_channel_flash(struct gb_channel *channel) in is_channel_flash() argument
79 return !!(channel->mode & (GB_CHANNEL_MODE_FLASH | GB_CHANNEL_MODE_TORCH in is_channel_flash()
90 static struct led_classdev *get_channel_cdev(struct gb_channel *channel) in get_channel_cdev() argument
92 return &channel->fled.led_cdev; in get_channel_cdev()
98 struct gb_channel *channel; in get_channel_from_mode() local
102 channel = &light->channels[i]; in get_channel_from_mode()
103 if (channel->mode == mode) in get_channel_from_mode()
[all …]
/linux-6.12.1/drivers/ipack/devices/
Dipoctal.c48 struct ipoctal_channel channel[NR_CHANNELS]; member
57 return container_of(chan, struct ipoctal, channel[index]); in chan_to_ipoctal()
60 static void ipoctal_reset_channel(struct ipoctal_channel *channel) in ipoctal_reset_channel() argument
62 iowrite8(CR_DISABLE_RX | CR_DISABLE_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
63 channel->rx_enable = 0; in ipoctal_reset_channel()
64 iowrite8(CR_CMD_RESET_RX, &channel->regs->w.cr); in ipoctal_reset_channel()
65 iowrite8(CR_CMD_RESET_TX, &channel->regs->w.cr); in ipoctal_reset_channel()
66 iowrite8(CR_CMD_RESET_ERR_STATUS, &channel->regs->w.cr); in ipoctal_reset_channel()
67 iowrite8(CR_CMD_RESET_MR, &channel->regs->w.cr); in ipoctal_reset_channel()
72 struct ipoctal_channel *channel; in ipoctal_port_activate() local
[all …]
/linux-6.12.1/drivers/phy/renesas/
Dr8a779f0-ether-serdes.c37 struct r8a779f0_eth_serdes_channel channel[R8A779F0_ETH_SERDES_NUM]; member
53 r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel, in r8a779f0_eth_serdes_reg_wait() argument
59 iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT); in r8a779f0_eth_serdes_reg_wait()
61 ret = readl_poll_timeout_atomic(channel->addr + offs, val, in r8a779f0_eth_serdes_reg_wait()
65 dev_dbg(&channel->phy->dev, in r8a779f0_eth_serdes_reg_wait()
67 __func__, channel->index, offs, bank, mask, expected); in r8a779f0_eth_serdes_reg_wait()
75 struct r8a779f0_eth_serdes_channel *channel; in r8a779f0_eth_serdes_common_init_ram() local
79 channel = &dd->channel[i]; in r8a779f0_eth_serdes_common_init_ram()
80 ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01); in r8a779f0_eth_serdes_common_init_ram()
91 r8a779f0_eth_serdes_common_setting(struct r8a779f0_eth_serdes_channel *channel) in r8a779f0_eth_serdes_common_setting() argument
[all …]
/linux-6.12.1/drivers/dma/sh/
Drz-dmac.c192 static void rz_dmac_ch_writel(struct rz_dmac_chan *channel, unsigned int val, in rz_dmac_ch_writel() argument
196 writel(val, channel->ch_base + offset); in rz_dmac_ch_writel()
198 writel(val, channel->ch_cmn_base + offset); in rz_dmac_ch_writel()
201 static u32 rz_dmac_ch_readl(struct rz_dmac_chan *channel, in rz_dmac_ch_readl() argument
205 return readl(channel->ch_base + offset); in rz_dmac_ch_readl()
207 return readl(channel->ch_cmn_base + offset); in rz_dmac_ch_readl()
215 static void rz_lmdesc_setup(struct rz_dmac_chan *channel, in rz_lmdesc_setup() argument
220 channel->lmdesc.base = lmdesc; in rz_lmdesc_setup()
221 channel->lmdesc.head = lmdesc; in rz_lmdesc_setup()
222 channel->lmdesc.tail = lmdesc; in rz_lmdesc_setup()
[all …]
/linux-6.12.1/drivers/media/platform/allegro-dvt/
Dallegro-core.c285 /* user_id is used to identify the channel during CREATE_CHANNEL */
306 allegro_channel_get_i_frame_qp(struct allegro_channel *channel) in allegro_channel_get_i_frame_qp() argument
308 if (channel->codec == V4L2_PIX_FMT_HEVC) in allegro_channel_get_i_frame_qp()
309 return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_i_frame_qp); in allegro_channel_get_i_frame_qp()
311 return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_i_frame_qp); in allegro_channel_get_i_frame_qp()
315 allegro_channel_get_p_frame_qp(struct allegro_channel *channel) in allegro_channel_get_p_frame_qp() argument
317 if (channel->codec == V4L2_PIX_FMT_HEVC) in allegro_channel_get_p_frame_qp()
318 return v4l2_ctrl_g_ctrl(channel->mpeg_video_hevc_p_frame_qp); in allegro_channel_get_p_frame_qp()
320 return v4l2_ctrl_g_ctrl(channel->mpeg_video_h264_p_frame_qp); in allegro_channel_get_p_frame_qp()
324 allegro_channel_get_b_frame_qp(struct allegro_channel *channel) in allegro_channel_get_b_frame_qp() argument
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/
Ddma.txt4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
20 - reg : DMA channel specific registers
21 - cell-index : DMA channel index starts at 0.
24 - interrupts : interrupt specifier for DMA channel IRQ
38 dma-channel@0 {
39 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
45 dma-channel@80 {
46 compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
[all …]
/linux-6.12.1/drivers/most/
Dmost_snd.c28 * struct channel - private structure to keep channel specific data
31 * @iface: interface for which the channel belongs to
32 * @cfg: channel configuration
35 * @id: channel index
44 struct channel { struct
152 * get_channel - get pointer to channel
154 * @channel_id: channel ID
156 * This traverses the channel list and returns the channel matching the
159 * Returns pointer to channel on success or NULL otherwise.
161 static struct channel *get_channel(struct most_interface *iface, in get_channel()
[all …]
/linux-6.12.1/drivers/ptp/
Dptp_clockmatrix.c41 static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm);
242 static int arm_tod_read_trig_sel_refclk(struct idtcm_channel *channel, u8 ref) in arm_tod_read_trig_sel_refclk() argument
244 struct idtcm *idtcm = channel->idtcm; in arm_tod_read_trig_sel_refclk()
252 err = idtcm_write(idtcm, channel->tod_read_secondary, in arm_tod_read_trig_sel_refclk()
259 err = idtcm_write(idtcm, channel->tod_read_secondary, tod_read_cmd, in arm_tod_read_trig_sel_refclk()
273 static int idtcm_extts_enable(struct idtcm_channel *channel, in idtcm_extts_enable() argument
283 idtcm = channel->idtcm; in idtcm_extts_enable()
303 /* Use the pin configured for the channel */ in idtcm_extts_enable()
304 ref = ptp_find_pin(channel->ptp_clock, PTP_PF_EXTTS, channel->tod); in idtcm_extts_enable()
308 __func__, channel->tod); in idtcm_extts_enable()
[all …]
Dptp_idt82p33.c99 static int idt82p33_dpll_set_mode(struct idt82p33_channel *channel, in idt82p33_dpll_set_mode() argument
102 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_dpll_set_mode()
106 if (channel->pll_mode == mode) in idt82p33_dpll_set_mode()
109 err = idt82p33_read(idt82p33, channel->dpll_mode_cnfg, in idt82p33_dpll_set_mode()
118 err = idt82p33_write(idt82p33, channel->dpll_mode_cnfg, in idt82p33_dpll_set_mode()
123 channel->pll_mode = mode; in idt82p33_dpll_set_mode()
128 static int idt82p33_set_tod_trigger(struct idt82p33_channel *channel, in idt82p33_set_tod_trigger() argument
131 struct idt82p33 *idt82p33 = channel->idt82p33; in idt82p33_set_tod_trigger()
138 err = idt82p33_read(idt82p33, channel->dpll_tod_trigger, in idt82p33_set_tod_trigger()
151 return idt82p33_write(idt82p33, channel->dpll_tod_trigger, in idt82p33_set_tod_trigger()
[all …]
/linux-6.12.1/drivers/hsi/clients/
Dhsi_char.c66 * struct hsc_channel - hsi_char internal channel data
67 * @ch: channel number
68 * @flags: Keeps state of the channel (open/close, reading, writing)
116 static void hsc_add_tail(struct hsc_channel *channel, struct hsi_msg *msg, in hsc_add_tail() argument
121 spin_lock_irqsave(&channel->lock, flags); in hsc_add_tail()
123 spin_unlock_irqrestore(&channel->lock, flags); in hsc_add_tail()
126 static struct hsi_msg *hsc_get_first_msg(struct hsc_channel *channel, in hsc_get_first_msg() argument
132 spin_lock_irqsave(&channel->lock, flags); in hsc_get_first_msg()
140 spin_unlock_irqrestore(&channel->lock, flags); in hsc_get_first_msg()
161 static void hsc_reset_list(struct hsc_channel *channel, struct list_head *l) in hsc_reset_list() argument
[all …]
/linux-6.12.1/sound/xen/
Dxen_snd_front_evtchnl.c23 struct xen_snd_front_evtchnl *channel = dev_id; in evtchnl_interrupt_req() local
24 struct xen_snd_front_info *front_info = channel->front_info; in evtchnl_interrupt_req()
28 if (unlikely(channel->state != EVTCHNL_STATE_CONNECTED)) in evtchnl_interrupt_req()
31 mutex_lock(&channel->ring_io_lock); in evtchnl_interrupt_req()
34 rp = channel->u.req.ring.sring->rsp_prod; in evtchnl_interrupt_req()
43 for (i = channel->u.req.ring.rsp_cons; i != rp; i++) { in evtchnl_interrupt_req()
44 resp = RING_GET_RESPONSE(&channel->u.req.ring, i); in evtchnl_interrupt_req()
45 if (resp->id != channel->evt_id) in evtchnl_interrupt_req()
53 channel->u.req.resp_status = resp->status; in evtchnl_interrupt_req()
54 complete(&channel->u.req.completion); in evtchnl_interrupt_req()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dcirrus,ep9301-dma-m2p.yaml30 - description: m2p0 channel registers
31 - description: m2p1 channel registers
32 - description: m2p2 channel registers
33 - description: m2p3 channel registers
34 - description: m2p4 channel registers
35 - description: m2p5 channel registers
36 - description: m2p6 channel registers
37 - description: m2p7 channel registers
38 - description: m2p8 channel registers
39 - description: m2p9 channel registers
[all …]
/linux-6.12.1/drivers/scsi/qla2xxx/
Dqla_devtbl.h8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
17 "QCP2340", "cPCI to 2Gb FC, Single Channel", /* 0x109 */
[all …]
/linux-6.12.1/drivers/firmware/arm_scmi/transports/
Doptee.c24 * PTA_SCMI_CMD_CAPABILITIES - Get channel capabilities
34 * [in] value[0].a: Channel handle
37 * already identified and bound to channel handle in both SCMI agent
47 * [in] value[0].a: Channel handle
59 * PTA_SCMI_CMD_GET_CHANNEL - Get channel handle
63 * [in] value[0].a: Channel identifier
64 * [out] value[0].a: Returned channel handle
73 * [in] value[0].a: Channel handle
105 * struct scmi_optee_channel - Description of an OP-TEE SCMI channel
107 * @channel_id: OP-TEE channel ID used for this transport
[all …]
/linux-6.12.1/drivers/net/ipa/
Dgsi.c52 * of data to or from the IPA. A channel is implemented as a ring buffer,
59 * one or more TREs to a channel, the writer (either the IPA or an EE) writes
63 * Each channel has a GSI "event ring" associated with it. An event ring
64 * is implemented very much like a channel ring, but is always directed from
65 * the IPA to an EE. The IPA notifies an EE (such as the AP) about channel
66 * events by adding an entry to the event ring associated with the channel.
69 * to the channel TRE whose completion the event represents.
71 * Each TRE in a channel ring has a set of flags. One flag indicates whether
73 * an interrupt) in the channel's event ring. Other flags allow transfer
76 * to signal completion of channel transfers.
[all …]
/linux-6.12.1/drivers/hsi/controllers/
Domap_ssi_regs.h33 # define SSI_DATAACCEPT(channel) (1 << (channel)) argument
34 # define SSI_DATAAVAILABLE(channel) (1 << ((channel) + 8)) argument
35 # define SSI_DATAOVERRUN(channel) (1 << ((channel) + 16)) argument
40 # define SSI_GDD_LCH(channel) (1 << (channel)) argument
44 # define SSI_WAKE(channel) (1 << (channel)) argument
62 # define SSI_FULL(channel) (1 << (channel)) argument
71 #define SSI_SST_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
72 #define SSI_SST_SWAPBUF_CH_REG(channel) (0xc0 + ((channel) * 4)) argument
82 # define SSI_NOTEMPTY(channel) (1 << (channel)) argument
91 #define SSI_SSR_BUFFER_CH_REG(channel) (0x80 + ((channel) * 4)) argument
[all …]
/linux-6.12.1/drivers/net/wwan/iosm/
Diosm_ipc_imem_ops.c15 /* Open a packet data online channel between the network layer and CP. */
79 /* Initialize wwan channel */
142 /* return true if channel is ready for use */
144 struct ipc_mem_channel *channel) in ipc_imem_is_channel_active() argument
162 if (channel->state != IMEM_CHANNEL_RESERVED) { in ipc_imem_is_channel_active()
164 "ch[%d]:invalid channel state %d,expected %d", in ipc_imem_is_channel_active()
165 channel->channel_id, channel->state, in ipc_imem_is_channel_active()
174 channel->channel_id, phase); in ipc_imem_is_channel_active()
177 /* Check the full availability of the channel. */ in ipc_imem_is_channel_active()
178 if (channel->state != IMEM_CHANNEL_ACTIVE) { in ipc_imem_is_channel_active()
[all …]
/linux-6.12.1/sound/soc/codecs/
Dtas5086.c70 #define TAS5086_CHANNEL_VOL(X) (0x08 + (X)) /* Channel 1-6 volume */
537 SOC_DOUBLE_R_TLV("Channel 1/2 Playback Volume",
540 SOC_DOUBLE_R_TLV("Channel 3/4 Playback Volume",
543 SOC_DOUBLE_R_TLV("Channel 5/6 Playback Volume",
567 SOC_DAPM_ENUM("Channel 1 input", tas5086_dapm_input_mux_enum[0]),
568 SOC_DAPM_ENUM("Channel 2 input", tas5086_dapm_input_mux_enum[1]),
569 SOC_DAPM_ENUM("Channel 3 input", tas5086_dapm_input_mux_enum[2]),
570 SOC_DAPM_ENUM("Channel 4 input", tas5086_dapm_input_mux_enum[3]),
571 SOC_DAPM_ENUM("Channel 5 input", tas5086_dapm_input_mux_enum[4]),
572 SOC_DAPM_ENUM("Channel 6 input", tas5086_dapm_input_mux_enum[5]),
[all …]
/linux-6.12.1/Documentation/sound/designs/
Dchannel-mapping-api.rst2 ALSA PCM channel-mapping API
10 The channel mapping API allows user to query the possible channel maps
11 and the current channel map, also optionally to modify the channel map
14 A channel map is an array of position for each PCM channel.
15 Typically, a stereo PCM stream has a channel map of
17 while a 4.0 surround PCM stream has a channel map of
20 The problem, so far, was that we had no standard channel map
21 explicitly, and applications had no way to know which channel
29 was no way to specify this because of lack of channel map
30 specification. These are the main motivations for the new channel
[all …]

12345678910>>...197