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/linux-6.12.1/drivers/mtd/chips/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "RAM/ROM/Flash chip drivers"
6 tristate "Detect flash chips by Common Flash Interface (CFI) probe"
10 The Common Flash Interface specification was developed by Intel,
11 AMD and other flash manufactures that provides a universal method
12 for probing the capabilities of flash devices. If you wish to
13 support any device that is CFI-compliant, you need to enable this
14 option. Visit <https://www.amd.com/products/nvd/overview/cfi.html>
15 for more information on CFI.
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
[all …]
Dcfi_cmdset_0002.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
14 * XIP support hooks by Vitaly Wool (based on code for Intel flash
17 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
37 #include <linux/mtd/cfi.h>
52 * Status Register bit description. Used by flash devices that don't
118 * CFI Primary Vendor-Specific Extended Query table 1.5
120 static int cfi_use_status_reg(struct cfi_private *cfi) in cfi_use_status_reg() argument
122 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; in cfi_use_status_reg()
125 return extp && extp->MinorVersion >= '5' && in cfi_use_status_reg()
[all …]
Dcfi_util.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
23 #include <linux/mtd/cfi.h>
40 struct map_info *map, struct cfi_private *cfi) in cfi_build_cmd_addr() argument
43 unsigned interleave = cfi_interleave(cfi); in cfi_build_cmd_addr()
44 unsigned type = cfi->device_type; in cfi_build_cmd_addr()
62 * Transforms the CFI command for the given geometry (bus width & interleave).
66 map_word cfi_build_cmd(u_long cmd, struct map_info *map, struct cfi_private *cfi) in cfi_build_cmd() argument
85 chip_mode = map_bankwidth(map) / cfi_interleave(cfi); in cfi_build_cmd()
86 chips_per_word = wordwidth * cfi_interleave(cfi) / map_bankwidth(map); in cfi_build_cmd()
[all …]
Dcfi_cmdset_0001.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
10 * - completely revamped method functions so they are aware and
11 * independent of the flash geometry (buswidth, interleave, etc.)
12 * - scalability vs code size is completely set at compile-time
13 * (see include/linux/mtd/cfi.h for selection)
14 * - optimized write buffer method
16 * - reworked lock/unlock/erase support for var size flash
18 * - auto unlock sectors on resume for auto locking flash on power up
37 #include <linux/mtd/cfi.h>
[all …]
Dcfi_probe.c1 // SPDX-License-Identifier: GPL-2.0
3 Common Flash Interface probe code.
19 #include <linux/mtd/cfi.h>
29 unsigned long *chip_map, struct cfi_private *cfi);
30 static int cfi_chip_setup(struct map_info *map, struct cfi_private *cfi);
46 #define xip_enable(base, map, cfi) \ argument
48 cfi_qry_mode_off(base, map, cfi); \
52 #define xip_disable_qry(base, map, cfi) \ argument
55 cfi_qry_mode_on(base, map, cfi); \
62 #define xip_enable(base, map, cfi) do { } while (0) argument
[all …]
Dgen_probe.c1 // SPDX-License-Identifier: GPL-2.0
3 * Routines common to all CFI-type probes.
4 * (C) 2001-2003 Red Hat, Inc.
12 #include <linux/mtd/cfi.h>
19 struct cfi_private *cfi);
24 struct cfi_private *cfi; in mtd_do_chip_probe() local
26 /* First probe the map to see if we have CFI stuff there. */ in mtd_do_chip_probe()
27 cfi = genprobe_ident_chips(map, cp); in mtd_do_chip_probe()
29 if (!cfi) in mtd_do_chip_probe()
32 map->fldrv_priv = cfi; in mtd_do_chip_probe()
[all …]
Dcfi_cmdset_0020.c1 // SPDX-License-Identifier: GPL-2.0
3 * Common Flash Interface support:
9 * - completely revamped method functions so they are aware and
10 * independent of the flash geometry (buswidth, interleave, etc.)
11 * - scalability vs code size is completely set at compile-time
12 * (see include/linux/mtd/cfi.h for selection)
13 * - optimized write buffer method
14 * 06/21/2002 Joern Engel <joern@wh.fh-wedel.de> and others
15 * - modified Intel Command Set 0x0001 to support ST Advanced Architecture
17 * - added a writev function
[all …]
/linux-6.12.1/drivers/mtd/maps/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 bool "Support non-linear mappings of flash chips"
10 paged mappings of flash chips.
13 tristate "Flash device in physical memory map"
16 This provides a 'mapping' driver which allows the NOR Flash and
19 the physical address and size of the flash chips on your
21 with config options or at run-time.
38 hex "Physical start address of flash mapping"
42 This is the physical memory location at which the flash chips
48 hex "Physical length of flash mapping"
[all …]
Dscb2_flash.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MTD map driver for BIOS Flash on Intel SCB2 boards
20 * * D8-D15 ignored
25 * logical address 0 hit higher-address sections of the chip, not physical 0.
29 * This driver assumes the chip is not write-protected by an external signal.
33 * updates for this board include 10 related (*.bio - &.bi9) binary files and
40 * offset 0x00000 to 0x4ffff (320k): unknown - SCSI BIOS, etc?
54 #include <linux/mtd/cfi.h>
66 .name = "SCB2 BIOS Flash",
76 struct map_info *map = mtd->priv; in scb2_fixup_mtd()
[all …]
Dsbc_gxx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* sbc_gxx.c -- MTD map driver for Arcom Control Systems SBC-MediaGX,
3 SBC-GXm and SBC-GX1 series boards.
8 The SBC-MediaGX / SBC-GXx has up to 16 MiB of
11 This driver uses the CFI probe and Intel Extended Command Set drivers.
13 The flash is accessed as follows:
15 16 KiB memory window at 0xdc000-0xdffff
20 bit 0-7: address bit 14-21
22 bit 0-1: address bit 22-23
23 bit 7: 0 - reset/powered down
[all …]
Dnettel.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * nettel.c -- mappings for NETtel/SecureEdge/SnapGear (x86) boards.
7 * (C) Copyright 2000-2001, Greg Ungerer (gerg@snapgear.com)
8 * (C) Copyright 2001-2002, SnapGear (www.snapgear.com)
20 #include <linux/mtd/cfi.h>
48 ((((size)-(64*1024)) >> SC520_PAR_SIZE_SHIFT) & SC520_PAR_SIZE_MASK) | \
140 * Set the Intel flash back to read mode since some old boot
145 struct cfi_private *cfi = nettel_intel_map.fldrv_priv; in nettel_reboot_notifier() local
148 /* Make sure all FLASH chips are put back into read mode */ in nettel_reboot_notifier()
150 cfi_send_gen_cmd(0xff, 0x55, b, &nettel_intel_map, cfi, in nettel_reboot_notifier()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mtd/
Dmtd-physmap.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
13 Flash chips (Memory Technology Devices) are often used for solid state
17 - $ref: mtd.yaml#
18 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
23 - items:
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/fsl/
Dfsl,ifc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FSL/NXP Integrated Flash Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 NXP's integrated flash controller (IFC) is an advanced version of the
16 external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
21 pattern: "^memory-controller@[0-9a-f]+$"
26 "#address-cells":
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dmedia5200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 &gpt0 { fsl,has-wdt; };
24 stdout-path = &console;
29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
68 phy-handle = <&phy0>;
72 phy0: ethernet-phy@0 {
[all …]
/linux-6.12.1/drivers/media/pci/cobalt/
Dcobalt-flash.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cobalt NOR flash functions
5 * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
11 #include <linux/mtd/cfi.h>
14 #include "cobalt-flash.h"
19 .name = "cobalt-flash",
29 r.x[0] = cobalt_bus_read32(map->virt, ADRS(offset)); in flash_read16()
43 cobalt_bus_write16(map->virt, ADRS(offset), data); in flash_write16()
54 data = cobalt_bus_read32(map->virt, ADRS(src)); in flash_copy_from()
59 len--; in flash_copy_from()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Drenesas,rpc-if.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Reduced Pin Count Interface (RPC-IF)
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
13 Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
16 The flash chip itself should be represented by a subnode of the RPC-IF node.
17 The flash interface is selected based on the "compatible" property of this
19 - if it contains "jedec,spi-nor", then SPI is used;
[all …]
Darm,pl172.txt5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/fsl/
Dgef_ppc9a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
40 /* flash@0,0 is a mirror of part of the memory in flash@1,0
41 flash@0,0 {
[all …]
Dgef_sbc610.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe8000000 0x08000000 // Paged Flash 0
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
40 /* flash@0,0 is a mirror of part of the memory in flash@1,0
41 flash@0,0 {
[all …]
Dgef_sbc310.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
31 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
32 1 0 0xe0000000 0x08000000 // Paged Flash 0
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
37 /* flash@0,0 is a mirror of part of the memory in flash@1,0
38 flash@0,0 {
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Dorion5x-rd88f5182-nas.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "orion5x-mv88f5182.dtsi"
11 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
20 stdout-path = &uart0;
30 gpio-leds {
31 compatible = "gpio-leds";
32 pinctrl-0 = <&pmx_debug_led>;
[all …]
/linux-6.12.1/drivers/mtd/lpddr/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Support for LPDDR flash chips"
10 flash chips. Synonymous with Mobile-DDR. It is a new standard for
11 DDR memories, intended for battery-operated systems.
15 tristate "Detect flash chips by QINFO probe"
19 families of devices. This serves similar purpose of CFI on legacy
20 Flash products
25 tristate "Support for LPDDR2-NVM flash chips"
27 This option enables support of PCM memories with a LPDDR2-NVM
/linux-6.12.1/arch/xtensa/boot/dts/
Dxtfpga-flash-4m.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 flash: flash@08000000 { label
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "cfi-flash";
9 bank-width = <2>;
10 device-width = <2>;
Dxtfpga-flash-16m.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 flash: flash@08000000 { label
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "cfi-flash";
9 bank-width = <2>;
10 device-width = <2>;
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr7s72100-genmai.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-14 Renesas Solutions Corp.
6 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
24 stdout-path = "serial0:115200n8";
32 flash@18000000 {
33 compatible = "mtd-rom";
35 bank-width = <4>;
[all …]

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