Searched +full:can +full:- +full:clock +full:- +full:select (Results 1 – 25 of 1032) sorted by relevance
12345678910>>...42
| /linux-6.12.1/drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
14 select HAVE_CLK
16 Select this option when the clock API in <linux/clk.h> is implemented
18 code should select COMMON_CLK instead and not define a custom
22 bool "Common Clock Framework"
24 select HAVE_CLK_PREPARE
25 select HAVE_CLK
26 select RATIONAL
28 The common clock framework is a single definition of struct
[all …]
|
| /linux-6.12.1/drivers/rtc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 select RTC_LIB
14 bool "Real Time Clock"
17 select RTC_LIB
29 If you say yes here, the system time (wall clock) will be set using
39 clock, usually rtc0. Initialization is done when the system
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
46 system will need an external clock source (like an NTP server).
48 If the clock you specify here is not battery backed, it may still
[all …]
|
| /linux-6.12.1/Documentation/arch/m68k/ |
| D | buddha-driver.rst | 8 ------------------------------------------------------------------------
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
41 $0-$7e Autokonfig-space, see Z-II docs.
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
6 can be accessed at any given time via four chip selects with 64M byte access
7 per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
[all …]
|
| D | arm,pl172.txt | 5 - compatible: Must be "arm,primecell" and exactly one from
8 - reg: Must contains offset/length value for controller.
10 - #address-cells: Must be 2. The partition number has to be encoded in the
11 first address cell and it may accept values 0..N-1
12 (N - total number of partitions). The second cell is the
15 - #size-cells: Must be set to 1.
17 - ranges: Must contain one or more chip select memory regions.
19 - clocks: Must contain references to controller clocks.
21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
23 - clock-ranges: Empty property indicating that child nodes can inherit
[all …]
|
| D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
20 # We need a select here so we don't match all nodes with 'arm,primecell'
21 select:
26 - arm,pl353-smc-r2p1
[all …]
|
| /linux-6.12.1/drivers/ptp/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # PTP clock support configuration
6 menu "PTP clock support"
9 tristate "PTP clock support"
12 select PPS
13 select NET_PTP_CLASSIFY
17 standard defines a Precision Time Protocol (PTP), which can
20 time stamping units, it can be possible to achieve
24 devices. If you want to use a PTP clock, then you should
25 also enable at least one clock driver as well.
[all …]
|
| /linux-6.12.1/drivers/clk/baikal-t1/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
9 consists of multiple global clock domains, which can be reset by
12 configurable and fixed clock dividers. Enable this option to be able
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
19 select MFD_SYSCON
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
27 CPUs, DDR, etc.) or passed over the clock dividers to be only
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
32 actually select a mode.
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
38 input clock. Used to determine the XI input clock.
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/bus/ |
| D | nvidia,tegra20-gmi.txt | 4 external memory. Can be used to attach various high speed devices such as
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
[all …]
|
| /linux-6.12.1/arch/m68k/ |
| D | Kconfig.cpu | 1 # SPDX-License-Identifier: GPL-2.0
13 applications, and are all System-On-Chip (SOC) devices, as opposed
17 MC68xxx processor, select M68KCLASSIC.
19 processor, select COLDFIRE.
23 select HAVE_ARCH_PFN_VALID
27 select CPU_HAS_NO_BITFIELDS
28 select CPU_HAS_NO_CAS
29 select CPU_HAS_NO_MULDIV64
30 select GENERIC_CSUM
31 select GPIOLIB
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ti/ |
| D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC.
3 The ATL IP is used to generate clock to be used to synchronize baseband and
4 audio codec. A single ATL IP provides four ATL clock instances sharing the same
5 functional clock but can be configured to provide different clocks.
6 ATL can maintain a clock averages to some desired frequency based on the bws/aws
7 signals - can compensate the drift between the two ws signal.
9 In order to provide the support for ATL and its output clocks (which can be used
12 Clock tree binding:
13 This binding uses the common clock binding[1].
14 To be able to integrate the ATL clocks with DT clock tree.
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/freescale/enetc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
8 If compiled as module (M), the module name is fsl-enetc-core.
13 select MDIO_DEVRES
14 select FSL_ENETC_CORE
15 select FSL_ENETC_IERB
16 select FSL_ENETC_MDIO
17 select PHYLINK
18 select PCS_LYNX
19 select DIMLIB
25 If compiled as module (M), the module name is fsl-enetc.
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7124.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Stefan Popa <stefan.popa@analog.com>
14 Bindings for the Analog Devices AD7124 ADC device. Datasheet can be
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7124-8.pdf
21 - adi,ad7124-4
22 - adi,ad7124-8
25 description: SPI chip select number for the device
30 description: phandle to the master clock (mclk)
[all …]
|
| D | adi,ad4130.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Cosmin Tanislav <cosmin.tanislav@analog.com>
14 Bindings for the Analog Devices AD4130 ADC. Datasheet can be found here:
15 https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-8.pdf
20 - adi,ad4130
27 description: phandle to the master clock (mclk)
29 clock-names:
31 - const: mclk
[all …]
|
| D | adi,ad7173.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ceclan Dumitru <dumitru.ceclan@analog.com>
15 The AD717x family offer a complete integrated Sigma-Delta ADC solution which
16 can be used in high precision, low noise single channel applications
18 (Factory Automation PLC Input modules). The Sigma-Delta ADC is intended
23 The AD411X family encompasses a series of low power, low noise, 24-bit,
24 sigma-delta analog-to-digital converters that offer a versatile range of
26 fully differential/single-ended and bipolar voltage inputs.
[all …]
|
| /linux-6.12.1/drivers/devfreq/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 select PM_OPP
7 devfreq, a generic DVFS framework can be registered for a device
11 Each device may have its own governor and policy. Devfreq can
16 However, because the clock frequencies of a single device are
19 clock frequency of the device, which is also attached
20 to a device by 1-to-1. The device registering devfreq takes the
22 to set its every clock accordingly with the "target" callback
39 Simple-Ondemand should be able to provide busy/total counter
81 select DEVFREQ_GOV_SIMPLE_ONDEMAND
[all …]
|
| /linux-6.12.1/arch/sh/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 select ARCH_32BIT_OFF_T
5 select ARCH_HAS_CPU_CACHE_ALIASING
6 select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A)
7 select ARCH_HAS_BINFMT_FLAT if !MMU
8 select ARCH_HAS_CPU_FINALIZE_INIT
9 select ARCH_HAS_CURRENT_STACK_POINTER
10 select ARCH_HAS_GIGANTIC_PAGE
11 select ARCH_HAS_GCOV_PROFILE_ALL
12 select ARCH_HAS_PTE_SPECIAL
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/net/can/ |
| D | renesas,rcar-can.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN Controller
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,can-r8a7778 # R-Car M1-A
18 - renesas,can-r8a7779 # R-Car H1
[all …]
|
| /linux-6.12.1/drivers/mfd/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 select IRQ_DOMAIN
16 select MFD_CORE
25 select MFD_CORE
26 select REGMAP_I2C
32 the core APIs _only_, you have to select individual components like
38 select REGMAP_SPI
39 select MFD_CORE
49 select MFD_SYSCON
51 Select this to get System Manager support for all Altera branded
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/spi/ |
| D | brcm,bcm63xx-hsspi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Zhang <william.zhang@broadcom.com>
11 - Kursad Oney <kursad.oney@broadcom.com>
12 - Jonas Gorski <jonas.gorski@gmail.com>
19 brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required to
20 use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
23 This rev 1.0 controller has a limitation that can not keep the chip select line
[all …]
|
| D | fsl-spi.txt | 4 - cell-index : QE SPI subblock index.
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - cs-gpios : specifies the gpio pins to be used for chipselects.
20 If unspecified, a single SPI device without a chip select can be used.
21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
22 SPISEL_BOOT signal is used as chip select for a slave device. Use
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/timer/ |
| D | arm,sp804.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Haojian Zhuang <haojian.zhuang@linaro.org>
14 16 or 32 bit operation and capable of running in one-shot, periodic, or
15 free-running mode. The input clock is shared, but can be gated and prescaled
18 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
21 # Need a custom select here or 'arm,primecell' will match on lots of nodes
22 select:
27 - arm,sp804
[all …]
|
| /linux-6.12.1/drivers/phy/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
15 API by which phy drivers can create PHY using the phy framework and
16 phy users can obtain reference to the PHY. All the users of this
17 framework should select this config.
21 select GENERIC_PHY
23 Generic MIPI D-PHY support.
25 Provides a number of helpers a core functions for MIPI D-PHY
32 select GENERIC_PHY
37 care of enabling and clock setup.
42 select GENERIC_PHY
[all …]
|
| /linux-6.12.1/arch/arm/mach-at91/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 select ARM_CPU_SUSPEND if PM && ARCH_MULTI_V7
7 select COMMON_CLK_AT91
8 select GPIOLIB
9 select PINCTRL
10 select SOC_BUS
14 bool "SAM Cortex-M7 family" if ARM_SINGLE_ARMV7M
15 select COMMON_CLK_AT91
16 select PINCTRL_AT91
18 Select this if you are using an SoC from Microchip's SAME7, SAMS7 or SAMV7
[all …]
|
12345678910>>...42