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/linux-6.12.1/drivers/staging/rtl8723bs/include/
Dhal_pwr_seq.h48 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x…
56 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable fallin…
57 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 …
58 …{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1…
60 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR …
69 …{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1…
71 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 …
72 …SK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x…
87 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power s…
94 …WR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power s…
[all …]
Drtw_ht.h65 #define LDPC_HT_ENABLE_TX BIT1
69 #define STBC_HT_ENABLE_TX BIT1
73 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
Ddrv_types.h119 /* BIT1 - 40MHz, 1: support, 0: non-support */
123 …/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT L…
125 …/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT S…
127 …/* BIT0: Enable VHT Beamformer, BIT1: Enable VHT Beamformee, BIT4: Enable HT Beamformer, BIT5: En…
452 #define DF_RX_BIT BIT1
Dhal_com_reg.h221 #define RRSR_2M BIT1
293 #define RCR_APM BIT1 /* Accept physical match packet */
548 #define SDIO_HIMR_AVAL_MSK BIT1
552 #define SDIO_HISR_AVAL BIT1
597 #define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
66 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
69 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
173 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
[all …]
/linux-6.12.1/include/linux/
Dmman.h130 * (x & bit1) ? bit2 : 0
132 * ("bit1" and "bit2" must be single bits)
134 #define _calc_vm_trans(x, bit1, bit2) \ argument
135 ((!(bit1) || !(bit2)) ? 0 : \
136 ((bit1) <= (bit2) ? ((x) & (bit1)) * ((bit2) / (bit1)) \
137 : ((x) & (bit1)) / ((bit1) / (bit2))))
/linux-6.12.1/Documentation/driver-api/mtd/
Dnand_ecc.rst45 byte 0: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp4 ... rp14
46 byte 1: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp2 rp4 ... rp14
47 byte 2: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp4 ... rp14
48 byte 3: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp4 ... rp14
49 byte 4: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp2 rp5 ... rp14
51 byte 254: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp0 rp3 rp5 ... rp15
52 byte 255: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 rp1 rp3 rp5 ... rp15
67 Similarly cp1 is the sum of all bit1, bit3, bit5 and bit7.
69 - cp2 is the parity over bit0, bit1, bit4 and bit5
71 - cp4 is the parity over bit0, bit1, bit2 and bit3.
[all …]
/linux-6.12.1/drivers/video/fbdev/via/
Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
346 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
561 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
606 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
672 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable()
744 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
/linux-6.12.1/Documentation/input/devices/
Dsentelic.rst38 Bit1 => Right Button, 1 is pressed, 0 is not pressed.
70 Bit1 => Right Button, 1 is pressed, 0 is not pressed.
75 Bit1 => the Vertical scrolling movement upward.
115 Bit1 => Right Button, 1 is pressed, 0 is not pressed.
119 Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
139 Bit1 => Right Button, 1 is pressed, 0 is not pressed.
170 Bit1 => 0
174 Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
195 Bit1 => 1
199 Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
[all …]
/linux-6.12.1/drivers/video/fbdev/
Dwm8505fb_regs.h17 * BIT1 GOVRH_VGA_YUV2RGB_ENABLE
26 * BIT1 GOVRH_DVO_YUV422
50 * BIT1 GOVRH_DVO_SYNC_POLAR
/linux-6.12.1/Documentation/leds/
Dleds-mlxcpld.rst53 [bit3,bit2,bit1,bit0] or
98 [bit3,bit2,bit1,bit0] or
110 [bit3,bit2,bit1,bit0]:
/linux-6.12.1/arch/sh/include/cpu-sh2/cpu/
Dcache.h21 #define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */
25 #define CCR_CACHE_CB 0x04 /* CCR[bit1=0,bit2=0] */
/linux-6.12.1/drivers/gpu/drm/amd/amdkfd/
Dkfd_mqd_manager.c159 * cu_mask[0] bit1 -> se_mask[1] bit0 in mqd_symmetrically_map_cu_mask()
161 * cu_mask[0] bit4 -> se_mask[0] bit1 in mqd_symmetrically_map_cu_mask()
166 * cu_mask[0] bit1 -> se_mask[1] bit0 (SE1,SH0,CU0) in mqd_symmetrically_map_cu_mask()
171 * cu_mask[0] bit8 -> se_mask[0] bit1 (SE0,SH0,CU1) in mqd_symmetrically_map_cu_mask()
178 * cu_mask[0] bit1 -> XCC1 se_mask[0] bit0 (XCC1,SE0,SH0,CU0) in mqd_symmetrically_map_cu_mask()
/linux-6.12.1/drivers/scsi/
Ddc395x.h75 #define BIT1 0x00000002 macro
80 #define UNIT_INFO_CHANGED BIT1
86 #define SCSI_SUPPORT BIT1
122 #define RESET_DETECT BIT1
130 #define ABORTION BIT1
142 #define ABORT_DEV BIT1
166 #define SYNC_NEGO_DONE BIT1
341 /* and bit2,bit1,bit0 is defined as follows : */
353 /* and bit2,bit1,bit0 is defined as follows : */
365 /* and bit2,bit1,bit0 is defined as follows : */
[all …]
/linux-6.12.1/include/uapi/linux/
Dioam6.h61 bit1:1, member
98 bit1:1, member
/linux-6.12.1/tools/mm/
Dpage-types.c857 " bit1,bit2 (flags & (bit1|bit2)) != 0\n" in usage()
858 " bit1,bit2=bit1 (flags & (bit1|bit2)) == bit1\n" in usage()
859 " bit1,~bit2 (flags & (bit1|bit2)) == bit1\n" in usage()
860 " =bit1,bit2 flags == (bit1|bit2)\n" in usage()
/linux-6.12.1/Documentation/devicetree/bindings/usb/
Dmediatek,mtk-xhci.yaml172 bit1 for u3port1, ... etc
177 bit1 for u2port1, ... etc
/linux-6.12.1/arch/mips/math-emu/
Ddp_2008class.c24 * bit1 = QNAN in ieee754dp_2008class()
Dsp_2008class.c24 * bit1 = QNAN in ieee754sp_2008class()
/linux-6.12.1/fs/btrfs/tests/
Dextent-io-tests.c347 int bit, bit1; in check_eb_bitmap() local
350 bit1 = !!extent_buffer_test_bit(eb, 0, i); in check_eb_bitmap()
351 if (bit1 != bit) { in check_eb_bitmap()
364 bit1 = !!extent_buffer_test_bit(eb, i / BITS_PER_BYTE, in check_eb_bitmap()
366 if (bit1 != bit) { in check_eb_bitmap()
/linux-6.12.1/drivers/usb/mtu3/
Dmtu3.h154 * bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported
233 * disable u2port0, bit1==1 to disable u2port1,... etc,
236 * disable u3port0, bit1==1 to disable u3port1,... etc
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hpo/dcn31/
Ddcn31_hpo_dp_stream_encoder.c311 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ in dcn31_hpo_dp_stream_enc_set_stream_attribute()
313 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ in dcn31_hpo_dp_stream_enc_set_stream_attribute()
320 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ in dcn31_hpo_dp_stream_enc_set_stream_attribute()
322 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ in dcn31_hpo_dp_stream_enc_set_stream_attribute()
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn401/
Ddcn401_dio_stream_encoder.c622 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ in enc401_stream_encoder_dp_set_stream_attribute()
624 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ in enc401_stream_encoder_dp_set_stream_attribute()
631 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ in enc401_stream_encoder_dp_set_stream_attribute()
633 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ in enc401_stream_encoder_dp_set_stream_attribute()
/linux-6.12.1/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbt_precomp.h32 #define BIT1 0x00000002 macro

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