Searched +full:big +full:- +full:endian (Results 1 – 25 of 1014) sorted by relevance
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| /linux-6.12.1/Documentation/netlink/specs/ |
| D | nftables.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
4 protocol: netlink-raw
11 -
15 -
16 name: nfgen-family
18 -
21 -
22 name: res-id
23 byte-order: big-endian
25 -
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| D | ovs_flow.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
6 uapi-header: linux/openvswitch.h
12 -
13 name: ovs-header
18 -
19 name: dp-ifindex
24 -
25 name: ovs-flow-stats
28 -
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| D | tc.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
4 protocol: netlink-raw
12 -
16 -
19 -
23 -
26 -
29 -
32 -
35 -
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| D | nfsd.yaml | 1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 uapi-header: linux/nfsd_netlink.h
9 attribute-sets:
10 -
11 name: rpc-status
13 -
16 byte-order: big-endian
17 -
20 -
23 -
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| /linux-6.12.1/Documentation/devicetree/bindings/regmap/ |
| D | regmap.txt | 5 little-endian,
6 big-endian,
7 native-endian: See common-properties.txt for a definition
10 Regmap defaults to little-endian register access on MMIO based
12 architectures that typically run big-endian operating systems
13 (e.g. PowerPC), registers can be defined as big-endian and must
16 On SoCs that can be operated in both big-endian and little-endian
19 chips), "native-endian" is used to allow using the same device tree
23 Scenario 1 : a register set in big-endian mode.
27 big-endian;
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
27 - description: PHY module clock
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| /linux-6.12.1/drivers/usb/host/ |
| D | ehci-fsl.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc.
8 /* offsets for the non-ehci registers in the FSL SOC USB controller */
22 #define USBMODE_ES (1 << 2) /* (Big) Endian Select */
31 #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */
32 #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */
33 #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */
34 #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */
35 #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */
36 #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */
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| /linux-6.12.1/Documentation/devicetree/bindings/usb/ |
| D | generic-ehci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ehci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 - $ref: usb-hcd.yaml
14 - if:
19 const: ibm,usb-ehci-440epx
28 - items:
29 - enum:
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| D | generic-ohci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ohci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 - items:
16 - enum:
17 - allwinner,sun4i-a10-ohci
18 - allwinner,sun50i-a64-ohci
19 - allwinner,sun50i-h6-ohci
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| /linux-6.12.1/drivers/crypto/cavium/cpt/ |
| D | cpt_hw_types.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
30 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
42 * Address must be 16-byte aligned.
44 * sign-extended bit <48> for forward compatibility.
46 * grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
48 * For the SSO to not discard the add-work request, FPA_PF_MAP() must map
56 * work-queue entry that CPT submits work to SSO after all context,
60 * use a sign-extended bit <48> for forward compatibility.
76 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
80 #else /* Word 0 - Little Endian */
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| /linux-6.12.1/Documentation/devicetree/bindings/ |
| D | common-properties.txt | 5 ----------
13 - big-endian: Boolean; force big endian register accesses
15 know the peripheral always needs to be accessed in big endian (BE) mode.
16 - little-endian: Boolean; force little endian register accesses
18 peripheral always needs to be accessed in little endian (LE) mode.
19 - native-endian: Boolean; always use register accesses matched to the
20 endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
21 BE vmlinux -> ioread32be/iowrite32be). In this case no byte swaps
22 will ever be performed. Use this if the hardware "self-adjusts"
27 In such cases, little-endian is the preferred default, but it is not
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| /linux-6.12.1/Documentation/devicetree/bindings/i2c/ |
| D | i2c-mux-reg.txt | 1 Register-based I2C Bus Mux
7 - compatible: i2c-mux-reg
8 - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
10 * Standard I2C mux properties. See i2c-mux.yaml in this directory.
11 * I2C child bus nodes. See i2c-mux.yaml in this directory.
14 - reg: this pair of <offset size> specifies the register to control the mux.
15 The <offset size> depends on its parent node. It can be any memory-mapped
18 - little-endian: The existence indicates the register is in little endian.
19 - big-endian: The existence indicates the register is in big endian.
20 If both little-endian and big-endian are omitted, the endianness of the
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| /linux-6.12.1/drivers/crypto/marvell/octeontx/ |
| D | otx_cpt_hw_types.h | 1 /* SPDX-License-Identifier: GPL-2.0
154 * CPT OcteonTX VF MSI-X Vector Enumeration
155 * Enumerates the MSI-X interrupt vectors.
167 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
179 * Address must be 16-byte aligned.
181 * sign-extended bit <48> for forward compatibility.
183 * grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
185 * For the SSO to not discard the add-work request, FPA_PF_MAP() must map
193 * work-queue entry that CPT submits work to SSO after all context,
197 * use a sign-extended bit <48> for forward compatibility.
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| /linux-6.12.1/arch/arm/boot/dts/nxp/ls/ |
| D | ls1021a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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| /linux-6.12.1/arch/arm/include/asm/ |
| D | bitops.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Big endian support: Copyright 2001, Nicolas Pitre
34 * First, the atomic bitops. These use native endian.
123 #include <asm-generic/bitops/non-atomic.h>
126 * A note about Endian-ness.
127 * -------------------------
129 * When the ARM is put into big endian mode via CR15, the processor
132 * ------------ physical data bus bits -----------
135 * big byte 0 byte 1 byte 2 byte 3
137 * This means that reading a 32-bit word at address 0 returns the same
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| /linux-6.12.1/Documentation/devicetree/bindings/sound/ |
| D | fsl,spdif.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
20 - fsl,imx35-spdif
21 - fsl,vf610-spdif
22 - fsl,imx6sx-spdif
23 - fsl,imx8qm-spdif
24 - fsl,imx8qxp-spdif
25 - fsl,imx8mq-spdif
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| /linux-6.12.1/tools/testing/selftests/rseq/ |
| D | rseq-arm.h | 1 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
3 * rseq-arm.h
5 * (C) Copyright 2016-2022 - Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
9 * - ARM little endian
12 * value 0x5de3. This traps if user-space reaches this instruction by mistake,
14 * pointer to attacker-controlled code on rseq abort.
23 * little endian:
27 * - ARMv6+ big endian (BE8):
29 * ARMv6+ -mbig-endian generates mixed endianness code vs data: little-endian
30 * code and big-endian data. The data value of the signature needs to have its
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| /linux-6.12.1/kernel/bpf/preload/iterators/ |
| D | README | 2 If you change "iterators.bpf.c" do "make -j" in this directory to
3 rebuild "iterators.lskel-little-endian.h". Then, on a big-endian
4 machine, do "make -j big" in this directory to rebuild
5 "iterators.lskel-big-endian.h". Commit both resulting headers.
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| /linux-6.12.1/Documentation/devicetree/bindings/counter/ |
| D | ftm-quaddec.txt | 6 - compatible: Must be "fsl,ftm-quaddec".
7 - reg: Must be set to the memory region of the flextimer.
10 - big-endian: Access the device registers in big-endian mode.
14 compatible = "fsl,ftm-quaddec";
16 big-endian;
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| /linux-6.12.1/arch/arm/boot/compressed/ |
| D | big-endian.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/arch/arm/boot/compressed/big-endian.S
5 * Switch CPU into big endian mode.
12 orr r0, r0, #(1 << 7) @ enable big endian mode
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| /linux-6.12.1/Documentation/devicetree/bindings/display/ |
| D | sm501fb.txt | 7 - compatible : should be "smi,sm501".
8 - reg : contain two entries:
9 - First entry: System Configuration register
10 - Second entry: IO space (Display Controller register)
11 - interrupts : SMI interrupt to the cpu should be described here.
14 - mode : select a video mode:
15 <xres>x<yres>[-<bpp>][@<refresh>]
16 - edid : verbatim EDID data block describing attached display.
19 - little-endian: available on big endian systems, to
20 set different foreign endian.
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| D | fsl,dcu.txt | 4 - compatible: Should be one of
5 * "fsl,ls1021a-dcu".
6 * "fsl,vf610-dcu".
8 - reg: Address and length of the register set for dcu.
9 - clocks: Handle to "dcu" and "pix" clock (in the order below)
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names: Should be "dcu" and "pix"
13 See ../clocks/clock-bindings.txt for details.
14 - big-endian Boolean property, LS1021A DCU registers are big-endian.
15 - port Video port for the panel output
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| /linux-6.12.1/Documentation/devicetree/bindings/pwm/ |
| D | fsl,vf610-ftm-pwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/fsl,vf610-ftm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 SoC | FTM-PWM endianness
16 --------+-------------------
21 Please see ../regmap/regmap.txt for more detail about how to specify endian
25 - Frank Li <Frank.Li@nxp.com>
30 - fsl,vf610-ftm-pwm
31 - fsl,imx8qm-ftm-pwm
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| /linux-6.12.1/drivers/mtd/nand/raw/brcmnand/ |
| D | brcmnand.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
16 /* Special register offset constant to intercept a non-MMIO access
40 if (soc && soc->prepare_data_bus) in brcmnand_soc_data_bus_prepare()
41 soc->prepare_data_bus(soc, true, is_param); in brcmnand_soc_data_bus_prepare()
47 if (soc && soc->prepare_data_bus) in brcmnand_soc_data_bus_unprepare()
48 soc->prepare_data_bus(soc, false, is_param); in brcmnand_soc_data_bus_unprepare()
55 * bus endianness (i.e., big-endian CPU + big endian bus ==> native in brcmnand_readl()
56 * endian I/O). in brcmnand_readl()
58 * Other architectures (e.g., ARM) either do not support big endian, or in brcmnand_readl()
59 * else leave I/O in little endian mode. in brcmnand_readl()
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| /linux-6.12.1/include/crypto/ |
| D | gf128mul.h | 1 /* gf128mul.h - GF(2^128) multiplication functions
16 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
59 * http://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/gcm/gcm-revised-spec.pdf
61 * The elements of GF(2^128) := GF(2)[X]/(X^128-X^7-X^2-X^1-1) can
73 * in every byte in little-endian order and the bytes themselves also in
74 * little endian order. I will call this lle (little-little-endian).
81 * bytes also. This is bbe (big-big-endian). Now the buffer above
86 * Both of the above formats are easy to implement on big-endian
90 * format (bits are stored in big endian order and the bytes in little
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