Home
last modified time | relevance | path

Searched +full:bcm +full:- +full:sr (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/phy/broadcom/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_BCM63XX_USBH) += phy-bcm63xx-usbh.o
3 obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
4 obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
5 obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o
6 obj-$(CONFIG_PHY_BCM_NS_USB3) += phy-bcm-ns-usb3.o
7 obj-$(CONFIG_PHY_NS2_PCIE) += phy-bcm-ns2-pcie.o
8 obj-$(CONFIG_PHY_NS2_USB_DRD) += phy-bcm-ns2-usbdrd.o
9 obj-$(CONFIG_PHY_BRCM_SATA) += phy-brcm-sata.o
10 obj-$(CONFIG_PHY_BRCM_USB) += phy-brcm-usb-dvr.o
[all …]
Dphy-bcm-sr-usb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
127 void __iomem *regs = phy_cfg->regs; in bcm_usb_ss_phy_init()
131 offset = phy_cfg->offset; in bcm_usb_ss_phy_init()
158 void __iomem *regs = phy_cfg->regs; in bcm_usb_hs_phy_init()
161 offset = phy_cfg->offset; in bcm_usb_hs_phy_init()
177 void __iomem *regs = phy_cfg->regs; in bcm_usb_phy_reset()
180 offset = phy_cfg->offset; in bcm_usb_phy_reset()
182 if (phy_cfg->type == USB_HS_PHY) { in bcm_usb_phy_reset()
195 int ret = -EINVAL; in bcm_usb_phy_init()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dbrcm,iproc-clocks.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
25 - brcm,bcm63138-armpll
26 - brcm,cygnus-armpll
27 - brcm,cygnus-genpll
28 - brcm,cygnus-lcpll0
[all …]
/linux-6.12.1/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-clock.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/clock/bcm-sr.h>
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <50000000>;
42 #clock-cells = <0>;
43 compatible = "fixed-factor-clock";
45 clock-div = <2>;
46 clock-mult = <1>;
50 #clock-cells = <1>;
[all …]
/linux-6.12.1/drivers/clk/bcm/
Dclk-sr.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/bcm-sr.h>
12 #include "clk-iproc.h"
88 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll0_clk_init()
147 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll2_clk_init()
186 CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", sr_genpll3_clk_init);
236 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll4_clk_init()
275 iproc_pll_clk_setup(pdev->dev.of_node, in sr_genpll5_clk_init()
320 iproc_pll_clk_setup(pdev->dev.of_node, in sr_lcpll0_clk_init()
[all …]
/linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dchip.c1 // SPDX-License-Identifier: ISC
24 /* PL-368 DMP definitions */
246 regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh)); in brcmf_chip_sb_corerev()
247 core->rev = SBCOREREV(regdata); in brcmf_chip_sb_corerev()
256 ci = core->chip; in brcmf_chip_sb_iscoreup()
257 address = CORE_SB(core->pub.base, sbtmstatelow); in brcmf_chip_sb_iscoreup()
258 regdata = ci->ops->read32(ci->ctx, address); in brcmf_chip_sb_iscoreup()
270 ci = core->chip; in brcmf_chip_ai_iscoreup()
271 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL); in brcmf_chip_ai_iscoreup()
274 regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL); in brcmf_chip_ai_iscoreup()
[all …]
/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
[all …]