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/linux-6.12.1/Documentation/devicetree/bindings/cache/
Dbaikal,bt1-l2-ctl.yaml2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 $id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
8 title: Baikal-T1 L2-cache Control Block
14 By means of the System Controller Baikal-T1 SoC exposes a few settings to
16 to change the Tag, Data and Way-select RAM access latencies. Baikal-T1
22 const: baikal,bt1-l2-ctl
27 baikal,l2-ws-latency:
34 baikal,l2-tag-latency:
41 baikal,l2-data-latency:
56 compatible = "baikal,bt1-l2-ctl";
[all …]
/linux-6.12.1/drivers/clk/baikal-t1/
DKconfig3 bool "Baikal-T1 Clocks Control Unit interface"
7 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
13 to select Baikal-T1 CCU PLLs and Dividers drivers.
18 bool "Baikal-T1 CCU PLLs support"
22 Enable this to support the PLLs embedded into the Baikal-T1 SoC
31 bool "Baikal-T1 CCU Dividers support"
36 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
42 bool "Baikal-T1 CCU Resets support"
Dclk-ccu-div.c3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
9 * Baikal-T1 CCU Dividers clock driver
236 if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) in ccu_div_set_data()
238 else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) in ccu_div_set_data()
246 if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) in ccu_div_get_data()
248 else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) in ccu_div_get_data()
279 if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) { in ccu_div_create_data()
282 } else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) { in ccu_div_create_data()
473 { .compatible = "baikal,bt1-ccu-axi" },
474 { .compatible = "baikal,bt1-ccu-sys" },
[all …]
Dccu-rst.h3 * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU Resets interface driver
28 * @sys_regs: Baikal-T1 System Controller registers map.
39 * @sys_regs: Baikal-T1 System Controller registers map.
Dccu-pll.h3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU PLL interface driver
28 * @sys_regs: Baikal-T1 System Controller registers map.
50 * @sys_regs: Baikal-T1 System Controller registers map.
Dccu-div.h3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU Dividers interface driver
61 * @sys_regs: Baikal-T1 System Controller registers map.
90 * @sys_regs: Baikal-T1 System Controller registers map.
Dccu-rst.c3 * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
8 * Baikal-T1 CCU Resets interface driver
180 if (of_device_is_compatible(rst_init->np, "baikal,bt1-ccu-axi")) { in ccu_rst_hw_register()
183 } else if (of_device_is_compatible(rst_init->np, "baikal,bt1-ccu-sys")) { in ccu_rst_hw_register()
Dclk-ccu-pll.c3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
9 * Baikal-T1 CCU PLL clocks driver
232 { .compatible = "baikal,bt1-ccu-pll" },
277 CLK_OF_DECLARE_DRIVER(ccu_pll, "baikal,bt1-ccu-pll", ccu_pll_init);
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dbaikal,bt1-ccu-div.yaml2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
22 registers. Baikal-T1 CCU is logically divided into the next components:
32 | Baikal-T1 CCU |
83 are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
90 const: baikal,bt1-ccu-axi
125 - baikal,bt1-ccu-axi
126 - baikal,bt1-ccu-sys
[all …]
Dbaikal,bt1-ccu-pll.yaml2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
29 | Baikal-T1 CCU |
84 Baikal-T1 SoC System Controller its DT node is supposed to be a child of
89 const: baikal,bt1-ccu-pll
116 compatible = "baikal,bt1-ccu-pll";
/linux-6.12.1/Documentation/devicetree/bindings/bus/
Dbaikal,bt1-axi.yaml2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
8 title: Baikal-T1 AXI-bus
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
23 accessible by means of the Baikal-T1 System Controller.
31 const: baikal,bt1-axi
50 description: Phandle to the Baikal-T1 System Controller DT node
87 compatible = "baikal,bt1-axi", "simple-bus";
Dbaikal,bt1-apb.yaml2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
8 title: Baikal-T1 APB-bus
14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
27 const: baikal,bt1-apb
73 compatible = "baikal,bt1-apb", "simple-bus";
/linux-6.12.1/Documentation/devicetree/bindings/hwmon/
Dbaikal,bt1-pvt.yaml2 # Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 $id: http://devicetree.org/schemas/hwmon/baikal,bt1-pvt.yaml#
8 title: Baikal-T1 PVT Sensor
14 Baikal-T1 SoC provides an embedded process, voltage and temperature
43 This bindings describes the external Baikal-T1 PVT control interfaces
50 const: baikal,bt1-pvt
69 description: Baikal-T1 can be referenced as the CPU thermal-sensor
72 baikal,pvt-temp-offset-millicelsius:
94 compatible = "baikal,bt1-pvt";
100 baikal,pvt-temp-offset-millicelsius = <1000>;
/linux-6.12.1/drivers/memory/
Dbt1-l2-ctl.c3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
8 * Baikal-T1 CM2 L2-cache Control Block driver.
38 * struct l2_ctl - Baikal-T1 L2 Control block private data.
40 * @sys_regs: Baikal-T1 System Controller registers map.
49 * enum l2_ctl_stall - Baikal-T1 L2-cache-RAM stall identifier.
61 * struct l2_ctl_device_attribute - Baikal-T1 L2-cache device attribute.
200 ret = l2_ctl_of_parse_property(l2, L2_WS_STALL, "baikal,l2-ws-latency"); in l2_ctl_of_parse()
204 ret = l2_ctl_of_parse_property(l2, L2_TAG_STALL, "baikal,l2-tag-latency"); in l2_ctl_of_parse()
209 "baikal,l2-data-latency"); in l2_ctl_of_parse()
308 { .compatible = "baikal,bt1-l2-ctl" },
[all …]
/linux-6.12.1/drivers/hwmon/
Dbt1-pvt.h3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 Process, Voltage, Temperature sensor driver
17 /* Baikal-T1 PVT registers and their bitfields */
73 * when one is determined for Baikal-T1 SoC).
105 * enum pvt_sensor_type - Baikal-T1 PVT sensor types (correspond to each PVT
126 * enum pvt_clock_type - Baikal-T1 PVT clocks.
137 * struct pvt_sensor_info - Baikal-T1 PVT sensor informational structure
193 * struct pvt_hwmon - Baikal-T1 PVT private data
196 * @regs: pointer to the Baikal-T1 PVT registers region.
/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dbaikal,bt1-pcie.yaml4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
26 const: baikal,bt1-pcie
98 baikal,bt1-syscon:
101 Phandle to the Baikal-T1 System Controller DT node. It's required to
125 compatible = "baikal,bt1-pcie";
/linux-6.12.1/Documentation/devicetree/bindings/ata/
Dbaikal,bt1-ahci.yaml4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
21 const: baikal,bt1-ahci
86 compatible = "baikal,bt1-ahci";
/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dsnps,dw-apb-ssi.yaml30 - baikal,bt1-sys-ssi
79 - description: Baikal-T1 SPI Controller
80 const: baikal,bt1-ssi
81 - description: Baikal-T1 System Boot SPI Controller
82 const: baikal,bt1-sys-ssi
202 compatible = "baikal,bt1-sys-ssi";
/linux-6.12.1/drivers/mtd/maps/
Dphysmap-bt1-rom.c3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
8 * Baikal-T1 Physically Mapped Internal ROM driver
24 * Baikal-T1 SoC ROMs are only accessible by the dword-aligned instructions.
26 * Note there is no need in bothering with endianness, since both Baikal-T1
114 if (!of_device_is_compatible(np, "baikal,bt1-int-rom")) in of_flash_probe_bt1_rom()
/linux-6.12.1/drivers/spi/
Dspi-dw-bt1.c3 // Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
9 // Baikal-T1 DW APB SPI and System Boot SPI driver
179 * Baikal-T1 Normal SPI Controllers don't always keep up with full SPI in dw_spi_bt1_std_init()
199 * Baikal-T1 System Boot Controller is equipped with a mux, which in dw_spi_bt1_sys_init()
239 * Baikal-T1 System Boot SPI Controller doesn't keep up with the full in dw_spi_bt1_sys_init()
312 { .compatible = "baikal,bt1-ssi", .data = dw_spi_bt1_std_init},
313 { .compatible = "baikal,bt1-sys-ssi", .data = dw_spi_bt1_sys_init},
329 MODULE_DESCRIPTION("Baikal-T1 System Boot SPI Controller driver");
/linux-6.12.1/drivers/bus/
Dbt1-axi.c3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
8 * Baikal-T1 AXI-bus driver
35 * struct bt1_axi - Baikal-T1 AXI-bus private data
38 * @sys_regs: Baikal-T1 System Controller registers map.
277 { .compatible = "baikal,bt1-axi" },
292 MODULE_DESCRIPTION("Baikal-T1 AXI-bus driver");
DKconfig42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
57 bool "Baikal-T1 AXI-bus driver"
63 Baikal-T1 SoC. Traffic arbitration is done by means of DW AMBA 3 AXI
/linux-6.12.1/drivers/pci/controller/dwc/
Dpcie-bt1.c3 * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
9 * Baikal-T1 PCIe controller driver
28 /* Baikal-T1 System CCU control registers */
114 /* Baikal-T1 PCIe specific control registers */
130 /* Generic Baikal-T1 PCIe interface resources */
169 * Baikal-T1 MMIO space must be read/written by the dword-aligned
337 syscon_regmap_lookup_by_phandle(dev->of_node, "baikal,bt1-syscon"); in bt1_pcie_get_resources()
628 { .compatible = "baikal,bt1-pcie" },
644 MODULE_DESCRIPTION("Baikal-T1 PCIe driver");
/linux-6.12.1/include/dt-bindings/reset/
Dbt1-ccu.h3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU reset indices
/linux-6.12.1/include/dt-bindings/clock/
Dbt1-ccu.h3 * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
5 * Baikal-T1 CCU clock indices

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