Searched full:axi_clkgen (Results 1 – 2 of 2) sorted by relevance
| /linux-6.12.1/drivers/clk/ |
| D | clk-axi-clkgen.c | 56 struct axi_clkgen { struct
231 static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, in axi_clkgen_write() argument
234 writel(val, axi_clkgen->base + reg); in axi_clkgen_write()
237 static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, in axi_clkgen_read() argument
240 *val = readl(axi_clkgen->base + reg); in axi_clkgen_read()
243 static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) in axi_clkgen_wait_non_busy() argument
249 axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val); in axi_clkgen_wait_non_busy()
258 static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, in axi_clkgen_mmcm_read() argument
264 ret = axi_clkgen_wait_non_busy(axi_clkgen); in axi_clkgen_mmcm_read()
271 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); in axi_clkgen_mmcm_read()
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | adi,axi-clkgen.yaml | 14 The axi_clkgen IP core is a software programmable clock generator,
17 Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
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