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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dadi,axi-clkgen.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Michael Hennerich <michael.hennerich@analog.com>
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
31 maxItems: 2
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/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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/linux-6.12.1/drivers/clk/
Dclk-axi-clkgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AXI clkgen driver
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
10 #include <linux/clk-provider.h>
69 case 2: in axi_clkgen_lookup_filter()
143 d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); in axi_clkgen_calc_params()
144 d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()
147 fvco_min_fract = limits->fvco_min << fract_shift; in axi_clkgen_calc_params()
148 fvco_max_fract = limits->fvco_max << fract_shift; in axi_clkgen_calc_params()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 tristate "Clock driver for WM831x/2x PMICs"
40 Supports the clocking subsystem of the WM831x/2x series of
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
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